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Wafer alignment method

A wafer and alignment mark technology, applied in the field of integrated circuit manufacturing, can solve problems such as high cost and inability to use a lithography machine, and achieve the effects of low cost, effective alignment, and reduced difficulty

Inactive Publication Date: 2015-04-29
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] After the silicon wafers are bonded, graphics must be formed on the subsequent wafers, and the accuracy depends on the lithography machine to complete. However, the current mainstream method is to use the backside lithography machine or double-sided lithography machine to align the front wafer to achieve alignment. Accuracy, the disadvantage is that it needs to form an alignment mark on the back of the silicon wafer, and it needs to use blue film or other protective layer, and it needs to be removed later, so the cost is high, and the existing photolithography machine cannot be used

Method used

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Embodiment Construction

[0026] In order to have a more specific understanding of the technical content, characteristics and effects of the present invention, now in conjunction with the accompanying drawings, the present invention is described in detail as follows:

[0027] The alignment method between the wafer and the wafer of the present embodiment, its specific implementation process flow is as follows:

[0028] Step 1, form a thin layer of silicon dioxide on silicon wafer 1 with physical vapor deposition method, such as figure 1 shown.

[0029] The silicon wafer 1 has a diameter of 200 mm and a thickness of 725 microns. The silicon dioxide layer has a thickness of 100 angstroms.

[0030] Step 2, forming 9 groups of alignment marks with a grating period of 12 microns and a depth of 0.5 to 100 microns on the silicon wafer 1, and then removing the silicon dioxide layer, such as figure 2 shown.

[0031] Step 3, deposit a layer of metal on the silicon wafer 1, so that a layer of metal layer is ...

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Abstract

The invention discloses a wafer alignment method which comprises the following steps: (1), a thin oxide layer is deposited on a first wafer layer; (2), alignment marks are formed on the first wafer layer, and the thin oxide layer is removed; (3), a high-reflectivity material is deposited on the first wafer layer and fills alignment mark grooves; (4), reverse etching is adopted to remove the high-reflectivity material on the surface of the first wafer layer, and only the high-reflectivity material in the alignment mark grooves are remained; (5), a thermal oxide layer is grown on the first wafer layer; (6), an integrated circuit pattern required later is formed on the first wafer layer; (7), a second wafer layer and the first wafer layer are bonded; and (8), the alignment marks on the first wafer layer are detected by infrared rays of a mask aligner, and an integrated circuit pattern required later is formed on the second wafer layer through photo-etching. The photo-etched alignment mark grooves of the first wafer layer are filled with the material whose reflectivity is higher than that of silicon, so that the lithography alignment difficulty for upper and lower wafer layers is reduced, and the alignment accuracy is improved.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a wafer-to-wafer alignment method. Background technique [0002] Micro-Electro-Mechanical Systems (MEMS) is a multidisciplinary frontier research field developed on the basis of microelectronics technology. As far as the semiconductor industry is concerned, the integration of MEMS and production process technology will bring a great leap forward for the system single chip. In the future, it is expected to integrate subsystems such as audio, light, chemical analysis, pressure, and temperature sensing in a single chip, and develop chips with sensory functions such as human eyes, nose, ears, and skin; The ability to control is beyond the ability of the human body. [0003] At present, there are three main technologies commonly used to manufacture MEMS devices: [0004] The first is the method of using traditional mechanical processing methods represented by Japan, ...

Claims

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Application Information

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IPC IPC(8): H01L21/68H01L23/544B81C3/00
CPCH01L21/68B81C3/00H01L23/544
Inventor 孟鸿林王雷
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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