Manufacturing method for Schottky chip used for chip scale packaging
A chip-level packaging and manufacturing method technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as small on-resistance Schottky chips
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no. 1 example ）
[0039] Compared with the above two Schottky chips, image 3 is a cross-sectional view schematically showing the Schottky chip 11 in the first embodiment of the present invention. like image 3 As shown, the Schottky chip 11 includes a highly doped silicon substrate 2 having a first conductivity type, a lowly doped silicon epitaxial layer 3 formed on the front surface 2a of the highly doped silicon substrate 2, the The silicon epitaxial layer 3 also has the first conductivity type, the Schottky electrode 4 and the ohmic electrode 6 formed on the silicon epitaxial layer 3, and the Schottky electrode 4 and the ohmic electrode 6 formed on the silicon epitaxial layer 3 The insulating layer 7, the guard ring 41 arranged around the periphery of the Schottky electrode 4, the guard ring 41 has a second conductivity type opposite to the first conductivity type; wherein the Schottky electrode 4 is formed on silicon The Schottky barrier metal 42 on the epitaxial layer 3 and the anode me...
no. 2 example ）
[0052] Image 6 is a cross-sectional view schematically showing the Schottky chip 20 in this embodiment. like Image 6 As shown, the difference between the Schottky chip 20 in this embodiment and the Schottky chip 11 in the first embodiment is that the Schottky chip further includes: on the side edges of several grooves penetrating through the silicon epitaxial layer 3 , an isolation layer 62 is arranged between the conductive polysilicon 61 and the side edge of the trench; preferably, the isolation layer 62 is made of the same insulating material as the insulating layer, for example, silicon dioxide is used as the insulating layer 71, so that the insulating layer can At the same time as the formation of 71, the formation of the isolation layer 62 is completed, which reduces the process steps and saves the manufacturing cost of the device; preferably, the thickness of the silicon dioxide isolation layer is 400-3000 Å. However, the present invention is not limited to the isol...
example 1
[0063] This example is based on Figure 5 The method for manufacturing the Schottky chip 11 in the first embodiment of the present invention is illustrated, and the Schottky chip of this example is manufactured.
[0064] Specifically, in the silicon substrate preparation step, a heavily phosphorous-doped N-type silicon substrate with a crystal orientation of is used, and the resistivity is 0.0010Ω·cm.
[0065] Next, a silicon epitaxial layer was formed, and a lightly doped phosphorous-doped N-type conductive silicon epitaxial layer with crystal orientation was formed. The thickness of the silicon epitaxial layer was 3.6 μm, and the resistivity was 0.56 Ω·cm.
[0066] Next, the silicon dioxide of the primary oxide layer 500A is first grown by thermal oxidation, and then the silicon dioxide of the secondary oxide layer 5000A is formed by wet oxygen oxidation.
[0067] Next, using the silicon dioxide layer formed above as a hard mask, a rectangular trench is selectively etched...
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Abstract
Description
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