Preparation method and device of Si-Ge-Si heterogeneous Ge-based solid-state plasma PiN diode

A plasma and diode technology, which is applied in the field of plasma PiN diode preparation, can solve the problems of low integration, high implant dose and energy, and incompatibility, so as to improve injection efficiency and current, improve breakdown voltage, and suppress influence Effect

Inactive Publication Date: 2017-05-31
XIDIAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] At present, the materials used in PiN diodes used in plasma reconfigurable antennas at home and abroad are all bulk silicon materials. This material has the problem of low carrier mobility in the intrinsic region, which affects the carrier concentration in the intrinsic region of the PiN diode, and thus Affect its solid-state plasma concentration; and the P region and N region of this structure are mostly formed by implantation process, which requires a la

Method used

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  • Preparation method and device of Si-Ge-Si heterogeneous Ge-based solid-state plasma PiN diode
  • Preparation method and device of Si-Ge-Si heterogeneous Ge-based solid-state plasma PiN diode
  • Preparation method and device of Si-Ge-Si heterogeneous Ge-based solid-state plasma PiN diode

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Embodiment 1

[0051] See figure 1 , figure 1It is a flow chart of a method for manufacturing a Si-Ge-Si heterogeneous Ge-based solid-state plasma PiN diode according to an embodiment of the present invention. The method is suitable for preparing a GeOI-based lateral solid-state plasma PiN diode, and the GeOI lateral solid-state solid-state plasma Bulk PiN diodes are mainly used to make solid-state plasmonic antennas. The method comprises the steps of:

[0052] (a) selecting a GeOI substrate with a certain crystal orientation, and setting an isolation region in the GeOI substrate;

[0053] (b) etching the GeOI substrate to form a P-type trench and an N-type trench, and the depth of the P-type trench and the N-type trench is less than the thickness of the top layer Ge of the GeOI substrate;

[0054] (c) filling the P-type trench and the N-type trench, and forming a P-type active region and an N-type active region in the P-type trench and the N-type trench by using an ion implantation proce...

Embodiment 2

[0092] See Figure 2a-Figure 2r , Figure 2a-Figure 2r It is a schematic diagram of a method for preparing a Si-Ge-Si heterogeneous Ge-based solid-state plasma PiN diode according to an embodiment of the present invention. On the basis of the above-mentioned embodiment 1, the length of the prepared channel is 22nm (the length of the solid-state plasma region is 100 nm. Micron) heterogeneous Ge-based solid-state plasma PiN diode as an example to describe in detail, the specific steps are as follows:

[0093] Step 1, substrate material preparation steps:

[0094] (1a) if Figure 2a As shown, the (100) crystal orientation is selected, the doping type is p-type, and the doping concentration is 10 14 cm -3 A GeOI substrate sheet 101, the thickness of the top layer Ge is 50 μm;

[0095] (1b) if Figure 2b As shown, a first layer of SiO with a thickness of 40nm is deposited on a GeOI substrate by chemical vapor deposition (Chemical vapor deposition, CVD for short). 2 layer 201...

Embodiment 3

[0122] Please refer to image 3 , image 3 It is a schematic diagram of the device structure of the Si-Ge-Si heterogeneous Ge-based solid-state plasma PiN diode according to the embodiment of the present invention. The heterogeneous Ge-based solid-state plasma PiN diode adopts the above-mentioned figure 1 The preparation method shown is made, specifically, the heterogeneous Ge-based solid-state plasma PiN diode is prepared and formed on the GeOI substrate 301, and the P region 304 and the N region 305 of the PiN diode are located laterally between the P region 304 and the The I regions between the N regions 305 are located in the top layer Ge302 of the GeOI substrate. Wherein, the PiN diode can be isolated by STI deep trenches, that is, an isolation trench 303 is provided outside the P region 304 and the N region 305, and the depth of the isolation trench 303 is greater than or equal to the thickness of the top layer Ge302.

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Abstract

The invention relates to a preparation method and a device of a Si-Ge-Si heterogeneous Ge-based solid-state plasma PiN diode. The preparation method comprises the steps of selecting a GeOI substrate of a certain crystal orientation, and setting an isolation region in the GeOI substrate; etching the GeOI substrate to form a P type trench and an N type trench, wherein the depths of the P type trench and the N type trench are smaller than the thickness of top layer Ge of the GeOI substrate; filling the P type trench and the N type trench, and performing an ion implantation process to form a P type active region and an N type active region in the P type trench and the N type trench; and forming leads on the GeOI substrate to complete the preparation of the heterogeneous Ge-based solid-state plasma PiN diode. According to the embodiments, the high-performance heterogeneous Ge-based solid-state plasma PiN diode, which is applicable to formation of a solid-state plasma antenna, can be prepared and provided through a deep trench isolation technology and the ion implantation process.

Description

technical field [0001] The invention relates to the technical field of semiconductor device manufacturing, in particular to a method for preparing a Si-Ge-Si heterogeneous Ge-based solid-state plasma PiN diode and a device thereof. Background technique [0002] At present, the materials used in PiN diodes used in plasma reconfigurable antennas at home and abroad are all bulk silicon materials. This material has the problem of low carrier mobility in the intrinsic region, which affects the carrier concentration in the intrinsic region of the PiN diode, and thus Affect its solid-state plasma concentration; and the P region and N region of this structure are mostly formed by implantation process, which requires a large implant dose and energy, high requirements on equipment, and is incompatible with existing processes; and the diffusion process, Although the junction depth is deep, the areas of the P region and the N region are large, the integration degree is low, and the dopi...

Claims

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Application Information

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IPC IPC(8): H01L21/329H01L29/868
CPCH01L29/868H01L29/6609
Inventor 胡辉勇王禹朱翔宇张鹤鸣宣荣喜舒斌宋建军苏汉苗渊浩
Owner XIDIAN UNIV
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