Perovskite/silicon heterojunction stacked solar cell structure and manufacturing method thereof

A stacked battery and silicon heterojunction technology, which is applied in circuits, photovoltaic power generation, electrical components, etc., can solve problems affecting the long-term stability of batteries, high cost, and difficulties in mass production of stacked batteries, and achieve high-efficiency metallization Solution, reduce battery production cost, improve the effect of battery stability

Pending Publication Date: 2018-08-24
嘉兴尚羿新能源有限公司
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  • Abstract
  • Description
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Problems solved by technology

However, the MoOx protective layer commonly used in previous processes was found to react with iodide ions in the perovskite layer, affecting the long-term stability of the battery.
[0003] In addition, the metallization process of traditional top-bottom batteries (thermal steaming, screen-printed gold/silver electrodes) is expensive, and the high process temperature makes it difficult to mass-pro

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  • Perovskite/silicon heterojunction stacked solar cell structure and manufacturing method thereof
  • Perovskite/silicon heterojunction stacked solar cell structure and manufacturing method thereof

Examples

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Specific Example 1

[0035] A manufacturing method of a perovskite / silicon heterojunction solar laminated battery structure includes the following steps:

[0036] Step 1: Fabricate the monocrystalline silicon layer 9. The n-type polished monocrystalline silicon substrate with a thickness of 90-250μm is etched in KOH solution to obtain the pyramid structure surface. The temperature of the solution is about 90°C. After the completion, the silicon wafer is cleaned. Here, the thickness of the n-type polished single crystal silicon substrate is preferably 150 μm.

[0037] Step 2: Plasma-enhanced chemical vapor deposition (PECVD) is used to sequentially deposit the intrinsic amorphous silicon film 10 and the p-type or n-type amorphous silicon film 11 on the back of the single crystal silicon layer 9. The thickness of the lower intrinsic amorphous silicon film 10 (a-Si:H(i)) is 3-10 nm, preferably 5 nm here; the p-type or n-type amorphous silicon film 11 is selected as an n-type amorphous ...

Example Embodiment

Specific Example 2

[0048] Step 1: Fabricate the monocrystalline silicon layer 9. The n-type polished monocrystalline silicon substrate with a thickness of 90-250μm is etched in KOH solution to obtain the pyramid structure surface. The temperature of the solution is about 90°C. After the completion, the silicon wafer is cleaned. Here, the thickness of the n-type polished single crystal silicon substrate is preferably 250 μm.

[0049] Step 2: Plasma-enhanced chemical vapor deposition (PECVD) is used to sequentially deposit the intrinsic amorphous silicon film 10 and the p-type or n-type amorphous silicon film 11 on the back of the single crystal silicon layer 9. The thickness of the lower intrinsic amorphous silicon film 10 (a-Si:H(i)) is 3-10 nm, preferably 5 nm here; the p-type or n-type amorphous silicon film 11 is selected as a p-type amorphous silicon film, p-type amorphous silicon film (a-Si:H(p + The thickness of )) is 3 to 30 nm, preferably 20 nm.

[0050] In step three, th...

Example Embodiment

Specific Example 3

[0060] Step 1: Fabricate the monocrystalline silicon layer 9. The n-type polished monocrystalline silicon substrate with a thickness of 90-250μm is etched in KOH solution to obtain the pyramid structure surface. The temperature of the solution is about 90°C. After the completion, the silicon wafer is cleaned. Here, the thickness of the n-type polished single crystal silicon substrate is preferably 250 μm.

[0061] Step 2: Plasma-enhanced chemical vapor deposition (PECVD) is used to sequentially deposit the intrinsic amorphous silicon film 10 and the p-type or n-type amorphous silicon film 11 on the back of the single crystal silicon layer 9. The thickness of the lower intrinsic amorphous silicon film 10 (a-Si:H(i)) is 3-10 nm, preferably 5 nm here; the p-type or n-type amorphous silicon film 11 is selected as a p-type amorphous silicon film, p-type amorphous silicon film (a-Si:H(p + The thickness of )) is 3 to 30 nm, preferably 20 nm.

[0062] In step three, th...

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Abstract

The invention discloses a perovskite/silicon heterojunction stacked solar cell structure, which comprises a top cell layer and a bottom cell layer arranged vertically, wherein a tunneling layer is arranged between the top cell layer and the bottom cell layer; the top cell layer comprises an upper transparent conductive film, an electron or hole transport layer, a mixed cation mixed halogen perovskite layer and a hole or electron transport layer arranged sequentially from the front surface to the back surface; and the bottom cell layer comprises an n-or p-type amorphous silicon film and an upper intrinsic amorphous silicon film, a single crystal silicon layer, a lower intrinsic amorphous silicon film, a p-type or n-type amorphous silicon film and a lower transparent conductive film arrangedsequentially from the front surface to the back surface. The invention also discloses a perovskite/silicon heterojunction stacked solar cell structure manufacturing method. According to the perovskite/silicon heterojunction stacked solar cell structure and the manufacturing method thereof, after the bottom cell amorphous silicon film is manufactured, a high temperature process does not need to beused and an independent perovskite protection layer does not need to be used either. While the technological process is shortened and extra cost is avoided, the cell stability is also enhanced.

Description

technical field [0001] The invention relates to a perovskite / silicon heterojunction solar stack cell structure and a manufacturing method thereof, belonging to the field of solar cell manufacturing. Background technique [0002] High-efficiency heterojunction cells (HJT) have the potential to challenge the commercial status of PERC cells in the next few years due to their simple structure, low light-induced attenuation, low temperature coefficient, high open-circuit voltage, and high conversion efficiency. However, the short-wave loss caused by its amorphous silicon layer will reduce its short-circuit current. Using a battery with a large band gap as the top battery and a HJT battery to form a stacked structure can improve the short-wave response of the battery and its theoretical conversion efficiency limit. The rapid development of perovskite batteries in recent years is obvious to all, and its conversion efficiency has soared from less than 4% in 2009 to 22.7% in 2017. ...

Claims

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Application Information

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IPC IPC(8): H01L31/043H01L31/0725H01L31/18H01L31/0224
CPCH01L31/022441H01L31/043H01L31/0725H01L31/1876Y02E10/50Y02P70/50
Inventor 邓晓帆姚宇李中天
Owner 嘉兴尚羿新能源有限公司
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