Oxide layer manufacturing method

Abstract

The invention discloses a method for manufacturing an oxide layer, comprising steps: step 1, providing a silicon wafer, and performing pretreatment on the surface of the silicon wafer; step 2, growing an oxide layer, including sub-steps: step 21, performing a pressure saturation process , the saturated gas is inert gas or nitrogen; during the heating process, the Si-H bond on the surface of the silicon wafer is broken and H2 is generated, and the H2 is blown out by the saturated gas; step 22, carry out the silicon dioxide deposition process, at a stable temperature and atmospheric pressure, the oxygen source gas reacts with silicon to form a silicon dioxide layer. The invention can improve the quality of the oxide layer and the interface quality between the oxide layer and the silicon surface, reduce the interface defects between the oxide layer and silicon, and improve the flicker noise of the device.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing an oxide layer. Background technique [0002] With the shrinking of device channel length and gate oxide thickness, especially the adoption of low-voltage power supply and nitrided gate dielectric layer technology, the effect of negative bias instability (NBTI) has gradually become an issue affecting 40nm One of the main factors of device reliability. The NBTI effect is caused by the increased negative gate voltage bias on the gate of the PMOS transistor at a high temperature usually greater than 100°C, and it is manifested in the continuous increase of the threshold voltage drift value, that is, ΔVth. This change is due to the negative Under the action of gate voltage and high temperature stress, the interface state and the positive charge of the oxide layer are formed at the Si-SiO2 gate interface. The Si in the Si-SiO2...

AI Technical Summary

Problems solved by technology

However, the introduction of nitrogen enhances the scattering of carriers in the channel, which intensifies the jitter of the channel current at low frequencies, thus increasing the flicker noise at low frequencies.

[0004] The increase of flicker noise causes lateral interference to the device at low frequencies, thus affecting the sensitivity at low frequencies

At present, logic devices in the industry, especially mobile phone chips, are gradually developing towards the SOC direction. The CPU, IO controller, Ram controller, audio circuit and even the baseband chip are all integrated on a single SOC. The existence of flicker noise will affect the clutter of the baseband. Under the filtering ability of the mobile phone, the call is not smooth under the weak signal of the mobile phone, which affects the effect

At the same time, the integrated audio circuit will seriously affect its signal-to-noise ratio (db) and affect the experience of mobile phones. Therefore, the industry's control over flicker noise is getting higher and higher.

Images