JCD integrated device based on P type epitaxy and preparation method thereof

Abstract

The invention relates to a JCD integrated device based on a P type epitaxy and a preparation method thereof, and belongs to the technical field of power semiconductor integration. The preparation method mainly comprises the following process steps of preparing a substrate; forming an N+ buried layer; growing a P type epitaxial layer; forming a penetration isolation region; preparing field oxygen;performing N trap injection and trap pushing; performing P trap injection and trap pushing; performing JFET grid electrode N type region injection and junction pushing; preparing gate oxygen and polycrystalline silicon; performing N+ injection; performing P+ injection; preparing ohm holes; performing annealing activation; performing deposition and etching a metal layer; integrating PJFET, CMOS, nLDMOS (and / or without) Poly resistors, Poly diodes, Poly capacitors and trap resistors into the same chip. The JCD integrated device provided by the invention has the advantages that the high-low voltage device compatibility is good; the isolation effect is good; the mask templates are few; the JFET has the advantages of high precision simulation features, great input impedance, high-speed, good anti-radiation features and the like; the integration of the low-voltage JEFT devices with high-voltage control DMOS parts and low-voltage logic CMOS parts is realized; the JCD integrated device can beapplied to the process design of the power source management IC, protection circuits and integrated operation amplifiers.

Description

Technical field [0001] The invention belongs to the technical field of power semiconductor integration, and specifically relates to a P-type epitaxy-based JCD integrated device and a preparation method thereof. Background technique [0002] For more than 40 years, semiconductor technology has been shrinking the feature size of chips along the route of Moore’s Law. However, the current semiconductor technology has developed to a bottleneck: as the line width becomes smaller and smaller, the manufacturing cost increases exponentially; and as the line width approaches At the nanometer scale, the quantum effect is becoming more and more obvious, and the leakage current of the chip is also increasing. Therefore, the development of semiconductor technology must consider the "post-Moore era" issue. In 2005, the international technology roadmap for semiconductors (ITRS) put forward the concept of more than Moore. Power semiconductor devices and power integration technology play a very ...

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Problems solved by technology

[0002]For more than 40 years, semiconductor technology has been shrinking the chip feature size along the route of Moore's Law. However, semiconductor technology has developed to a bottleneck: with the increasing line width The smaller the size, the manufacturing cost increases exponentially; and as the line width approaches the nanometer scale, the quantum effect becomes more and more obvious, and the leakage current of the chip becomes larger and larger

However, the integration technology of JFET devices still has many problems such as compatibility and poor performance of JFET devices.

Due to the particularity of the double-gate structure of the JFET device itself, there are still integration issues for the technical personnel to realize the monolithic integration of the low-voltage JFET, the high-voltage control part, and the low-voltage logic part, the compatibility of the high-voltage DMOS and the low-voltage JFET part, and the compatibility of the JFET and CMOS parts. Obstacles, due to the complex manufacturing process of JFET devices, its saturation characteristics and pinch-off characteristics are difficult to meet the application requirements at the same time, resulting in restrictions on the performance of JFET devices and the development of related integrated op amps

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