JCD integrated device integrated with VDMOS and preparation method thereof

A technology for integrating devices and device areas, which is applied in semiconductor/solid-state device manufacturing, electrical solid-state devices, semiconductor devices, etc., and can solve the problems of complex JFET device manufacturing process, rising manufacturing cost, and poor performance of compatible JFET devices.
CN109671707AActive Publication Date: 2019-04-23UNIV OF ELECTRONICS SCI & TECH OF CHINA
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
UNIV OF ELECTRONICS SCI & TECH OF CHINA
Publication Date
2019-04-23

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Abstract

The invention provides a JCD integrated device integrated with VDMOS and a preparation method thereof, and belongs to the technical field of power semiconductor integration. The manufacturing of JFET,CMOS and VDMOS on the same chip is realized by the invention for the first time; meanwhile, passive elements such as a poly capacitor, a poly resistor and a poly diode can be integrated with the JFET, CMOS and VDMOS to form a circuit. The advantages of high-switch speed and high voltage resistance of the VDMOS, excellent simulation characteristics, low-noise characteristics, temperature stabilityand anti-radiation capability of the JFET devices, high integrality of the CMOS part and the like are integrated by the invention; meanwhile, high flexibility is brought to the power circuit design.The whole process provided by the invention uses relatively few mask templates; the process level reusability is high; the manufacturing cost control is facilitated; the high-low-voltage compatibility, high performance, high efficiency and high reliability are realized on a limited chip area; the chip manufactured by using the JCD integration technology has good comprehensive performance and is favorable for the development of the single chip power system integration.
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Description

Technical field

[0001] The invention belongs to the technical field of power semiconductor integration, and specifically relates to a JCD integrated device integrating VDMOS and a preparation method thereof. Background technique

[0002] For more than 40 years, semiconductor technology has been shrinking the feature size of chips along the route of Moore’s Law. However, the current semiconductor technology has developed to a bottleneck: as the line width becomes smaller and smaller, the manufacturing cost increases exponentially; and as the line width approaches At the nanometer scale, the quantum effect is becoming more and more obvious, and the leakage current of the chip is also increasing. Therefore, the development of semiconductor technology must consider the "post-Moore era" issue. In 2005, the international technology roadmap for semiconductors (ITRS) put forward the concept of more than Moore. Power semiconductor devices and power integration technology play a very imp...

Claims

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