JCD integrated device integrated with VDMOS and preparation method thereof

Abstract

The invention provides a JCD integrated device integrated with VDMOS and a preparation method thereof, and belongs to the technical field of power semiconductor integration. The manufacturing of JFET,CMOS and VDMOS on the same chip is realized by the invention for the first time; meanwhile, passive elements such as a poly capacitor, a poly resistor and a poly diode can be integrated with the JFET, CMOS and VDMOS to form a circuit. The advantages of high-switch speed and high voltage resistance of the VDMOS, excellent simulation characteristics, low-noise characteristics, temperature stabilityand anti-radiation capability of the JFET devices, high integrality of the CMOS part and the like are integrated by the invention; meanwhile, high flexibility is brought to the power circuit design.The whole process provided by the invention uses relatively few mask templates; the process level reusability is high; the manufacturing cost control is facilitated; the high-low-voltage compatibility, high performance, high efficiency and high reliability are realized on a limited chip area; the chip manufactured by using the JCD integration technology has good comprehensive performance and is favorable for the development of the single chip power system integration.

Description

Technical field [0001] The invention belongs to the technical field of power semiconductor integration, and specifically relates to a JCD integrated device integrating VDMOS and a preparation method thereof. Background technique [0002] For more than 40 years, semiconductor technology has been shrinking the feature size of chips along the route of Moore’s Law. However, the current semiconductor technology has developed to a bottleneck: as the line width becomes smaller and smaller, the manufacturing cost increases exponentially; and as the line width approaches At the nanometer scale, the quantum effect is becoming more and more obvious, and the leakage current of the chip is also increasing. Therefore, the development of semiconductor technology must consider the "post-Moore era" issue. In 2005, the international technology roadmap for semiconductors (ITRS) put forward the concept of more than Moore. Power semiconductor devices and power integration technology play a very imp...

AI Technical Summary

Problems solved by technology

[0002]For more than 40 years, semiconductor technology has been shrinking the chip feature size along the route of Moore's Law. However, semiconductor technology has developed to a bottleneck: with the increasing line width The smaller the size, the manufacturing cost increases exponentially; and as the line width approaches the nanometer scale, the quantum effect becomes more and more obvious, and the leakage current of the chip becomes larger and larger

However, the integration technology of JFET devices still has many problems such as compatibility and poor performance of JFET devices.

Due to the particularity of the double-gate structure of the JFET device itself, there are still integration issues for the technical personnel to realize the monolithic integration of the low-voltage JFET, the high-voltage control part, and the low-voltage logic part, the compatibility of the high-voltage DMOS and the low-voltage JFET part, and the compatibility of the JFET and CMOS parts. Obstacles, due to the complex manufacturing process of JFET devices, its saturation characteristics and pinch-off characteristics are difficult to meet the application requirements at the same time, resulting in restrictions on the performance of JFET devices and the development of related integrated op amps

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