Groove chip embedding process

Abstract

The invention provides a groove chip embedding process which comprises the following steps: (a) providing a silicon wafer, etching a plurality of TSV holes in the upper surface of the silicon wafer toform a TSV region, then forming a first passivation layer, and forming a second passivation layer on the first passivation layer and a seed layer; (b) electroplating metal to enable the TSV holes tobe filled with the metal to form metal columns; (c) thinning the lower surface of the silicon wafer, and etching the groove; (d) forming a third passivation layer on the lower surface of the silicon wafer, and coating photoresist on the third passivation layer; (e) removing the third passivation layer, the metal column and the photoresist on the surface of the metal column; and (f) filling soldering tin at the bottom of the groove, embedding the chip, and removing temporary bonding to obtain the chip embedding structure. According to the technical scheme, the metal layer and the hard mask layer are added to the surface of the copper column during corrosion of the copper column, and the protective medium is added to the bottom of the copper column to serve as the height control layer, so that the copper column can be stopped in the protective medium after being corroded, the protective medium is removed, the copper column is exposed, and the height of the copper column is accurately controlled.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a groove chip embedding process. Background technique [0002] Millimeter wave radio frequency technology is developing rapidly in the semiconductor industry. It is widely used in high-speed data communications, automotive radar, airborne missile tracking systems, and space spectrum detection and imaging. It is expected that the market will reach 1.1 billion US dollars in 2018 and become an emerging industry. New applications put forward new requirements for the electrical performance, compact structure and system reliability of the product. For the wireless transmitting and receiving system, it cannot be integrated into the same chip (SOC) at present, so it is necessary to integrate different chips including the radio frequency unit , filters, power amplifiers, etc. are integrated into an independent system to realize the functions of transmitting and receiving signals. ...

AI Technical Summary

Problems solved by technology

[0003] The traditional packaging technology installs various functional chips and passive devices on the substrate, which occupies a large area and has poor reliability, which cannot meet the trend of miniaturization of the packaging system. Packaging SIP) uses TSV technology and cavity structure to integrate chips with different substrates and different functions, which can realize chip stacking and interconnection in a small area, greatly reducing the area of ​​functional parts and increasing their reliability , and more and more become the direction of future development of the industry

[0004] The bottom of the RF chip needs to be dissipated and connected to the ground, which requires the bottom of the chip to be contacted by TSV metal pillars. The back of the adapter board is used as the cavity, and the bottom of the TSV is used as the bottom of the cavity, and then interconnected. The depth of the TSV will be different, and the bottom will be uneven, which is not conducive to the grounding of the chip. If the TSV is used as a long pillar, then The TSV metal pillars are exposed by dry etching, and finally the metal pillars are removed by wet etching, leaving only the bottom metal pillars, so that the problem of TSV planarity can be ignored, which is the main realization of this type of structure in the future. However, in practical applications, because the corrosion of the metal pillar is an isotropic behavior, if the metal pillar at the bottom of the cavity is corroded, the part of the metal pillar that is corroded first will go deep into the cavity bottom, which is not conducive to subsequent bottom interconnection and heat dissipation

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