Unlock instant, AI-driven research and patent intelligence for your innovation.

Semiconductor packaging structure and packaging method

A packaging method and packaging structure technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of easily damaged rewiring layer, low quality of rewiring layer, cumbersome electroplating process, etc. , to achieve the effect of low cost, enhanced strength, reduced deformation and fracture

Pending Publication Date: 2021-06-25
ACM RES SHANGHAI
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a semiconductor packaging structure and packaging method, which are used to solve the problem of poor quality of the rewiring layer in the prior art, cumbersome electroplating process for a specific shape RDL structure, and rewiring problems. Layers are prone to damage during soldering to the package substrate

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor packaging structure and packaging method
  • Semiconductor packaging structure and packaging method
  • Semiconductor packaging structure and packaging method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0126] This embodiment provides a packaging method, please refer to Figure 10 , shown as a process flow diagram of the encapsulation method, including the following steps:

[0127] S1: Provide a substrate, and form a cured insulating polymer layer with openings on the substrate.

[0128] S2: forming a barrier layer to cover the top surface of the insulating polymer layer, the sidewall and the bottom surface of the opening;

[0129] S3: forming a conductive material layer on the surface of the barrier layer, the conductive material layer filling the opening and higher than the top surface of the insulating polymer layer;

[0130] S4: removing the portion of the conductive material layer and the barrier layer higher than the top surface of the insulating polymer layer, and the remaining conductive material layer in the opening constitutes a rewiring layer.

[0131] See first Figure 11 to Figure 13 , performing step S1 : providing a substrate 201 , forming a cured insulating...

Embodiment 2

[0166] This embodiment adopts basically the same technical solution as Embodiment 1, except that the redistribution layer formed in this embodiment has a stepped structure.

[0167] see Figure 19 , is shown as the process flow chart of this embodiment. Compared with Embodiment 1, because the rewiring layer to be formed has a stepped structure, a second glue coating is performed after the exposure and curing process. The technical solution of this embodiment is clarified through specific description below.

[0168] See first Figure 20 to Figure 24 , Execute step S1: provide a substrate 301 (incoming material), and form a cured insulating polymer layer with openings on the substrate.

[0169] Specifically, the substrate 301 may be a wafer-level substrate, in which an integrated circuit may be prefabricated. The material of the insulating polymer layer includes but not limited to polyimide photoresist, and the opening includes but not limited to wire slots and through holes. ...

Embodiment 3

[0199] This embodiment provides a semiconductor packaging structure, please refer to Figure 18 , is shown as a schematic diagram of the semiconductor package structure, including a substrate 201, an insulating polymer layer 202, a rewiring layer 206' and a barrier layer 205, wherein the insulating polymer layer 202 is located on the substrate 201, and the rewiring Layer 206 ′ is located in the insulating polymer layer 202 , and the barrier layer 205 is located at the interface of the rewiring layer 206 ′ and the insulating polymer layer 202 .

[0200] Specifically, the semiconductor packaging structure is manufactured using the packaging method described in Embodiment 1.

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
Login to View More

Abstract

The invention provides a semiconductor packaging structure and a packaging method. The method comprises the following steps that: a substrate is provided, and a solidified insulating polymer layer with an opening is formed on the substrate; a barrier layer is formed to cover a top surface of the insulating polymer layer, sidewalls of the opening and a bottom surface of the insulating polymer; a conductive material layer on the surface of the barrier layer is obtained based on barrier layer electroplating, the conductive material layer fills the opening and is higher than the top surface of the insulating polymer layer; and the conductive material layer and the part of the barrier layer higher than the top surface of the insulating polymer layer are removed, wherein the remaining conductive material layer in the opening forms a rewiring layer. According to the semiconductor packaging structure and packaging method, electrochemical electroplating, stress-free polishing and chemical mechanical polishing methods are used in the RDL forming process, the buffer effect of the insulating polymer layer is utilized, a bottom notch can be eliminated so as to enhance the strength of the RDL, the possibility that the RDL is damaged due to extrusion in the welding process can be reduced, the process steps of the step-shaped RDL structure can be effectively reduced, and the production cost is greatly reduced.

Description

technical field [0001] The invention belongs to the field of packaging of semiconductor integrated circuits, and relates to a semiconductor packaging structure and a packaging method. Background technique [0002] As automobiles and electronic products have higher and higher requirements on the performance, size, and reliability of chips, wafer-level packaging (Wafer Level Package, WLP) technology continues to break through and develop. From the perspective of technical characteristics, wafer-level packaging is mainly divided into two types: Fan-in (fan-in) and Fan-out (fan-out). The traditional WLP package mostly adopts the Fan-in type, which is applied to an integrated circuit (IC) with a small number of pins. However, with the increase in the number of IC signal output pins, the requirements for the pitch of solder balls tend to be stricter, and the printed circuit board structure requires adjustment of the size of the IC after packaging and the position of the signal ou...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/60H01L23/485
CPCH01L23/4824H01L24/03H01L2224/0231H01L2224/02331H01L2224/02379
Inventor 余齐兴金一诺王坚王晖
Owner ACM RES SHANGHAI