Through silicon via copper film polishing solution

A technology of polishing liquid and through-silicon vias, which is applied in the direction of polishing compositions containing abrasives, can solve the problems of unsatisfactory copper removal rate, poor biological friendliness, unfavorable cleaning process, etc., and achieve good CMP effect and surface consistency Good, high chelation complexation effect

Active Publication Date: 2021-12-14
博力思(天津)电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the patented polishing solution is used under acidic conditions, which is easy to corrode the machine, and requires a large concentration of oxidizing agents to obtain a large corrosion rate, and the copper removal rate is still not ideal. In addition, azoles are used as corrosion inhibitors. It is easy to combine the copper film into a dense molecular film, which is not conducive to the subsequent cleaning process, and has poor biological friendliness, which is not conducive to environmental protection

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0023] The composition and weight percent of the polishing liquid in this embodiment are as follows: silica sol abrasives with a particle size of 80±5nm, 60±5nm and 40±5nm, mixed in a ratio of 1:1:1: 0.5%; glycine and lysine 1 :1 Mixing: 10% (complex chelating ability in synergistic alkaline environment); Betaine: 0.20% (copper surface is smoother).

[0024] Corresponding experimental data: Polishing conditions: rotating speed of upper and lower polishing heads: 78 / 83rpm; polishing fluid flow rate: 300ml / min; polishing pressure: 1.5psi; copper removal rate is 5200A / min, tantalum removal rate is 310A / min, copper film roughness Sq is 2.8nm.

Embodiment 2

[0026] The composition and weight percent of the polishing liquid in this embodiment are as follows: silica sol abrasives with a particle size of 80 ± 5nm, 60 ± 5nm and 40 ± 5nm, mixed in a ratio of 1:1:1: 12%; glycine and lysine 1 :1 Blend: 10%; Betaine: 0.20%.

[0027] Corresponding experimental data: Polishing conditions: rotating speed of upper and lower polishing heads: 78 / 83rpm; polishing fluid flow rate: 300ml / min; polishing pressure: 1.5psi; copper removal rate is 30923A / min, tantalum removal rate is 960A / min, copper film roughness Sq is 3.2nm.

Embodiment 3

[0029]The composition and weight percentages of the polishing liquid in this embodiment are as follows: silica sol abrasives with a particle size of 80±5nm, 60±5nm and 40±5nm, mixed in a ratio of 1:1:1: 18%; glycine and lysine 1 :1 Blend: 10%; Betaine: 0.20%. Corresponding experimental data: Polishing conditions: rotating speed of upper and lower polishing heads: 78 / 83rpm; polishing liquid flow rate: 300ml / min; polishing pressure: 1.5psi; copper removal rate is 35160A / min, tantalum removal rate is 1468A / min, copper film roughness Sq is 10.8nm.

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Abstract

The invention relates to a through silicon via copper film polishing solution, which comprises an abrasive material, two or more chelating agents and a dish pit inhibitor, and is characterized in that the abrasive material is composed of large, medium and small particles mixed together according to a ratio, the particle size of the large particles is 70-120nm, the particle size of the medium particles is 50-80nm, the particle size of the small particles is 30-50nm, and the particles of the three grades are selected within the corresponding ranges according to an arithmetic progression mode during selection; and the chelating agent is a mixture of glycine and basic amino acid. In the CMP process, the polishing solution can quickly remove a copper film, and meanwhile, inhibit the step height between concave and convex platforms on the surface of the copper film.

Description

technical field [0001] The invention relates to a copper film polishing solution for through-silicon holes. Background technique [0002] Through-silicon via (Though Silicon Via, TSV) technology is a technology that vertically integrates multiple chips. 3D TSV wafers account for 9% of the total semiconductor market, and are the first choice for contact image sensors (Contact Image Sensor, CIS) and high-end memories. Connecting solutions, realizing the heterogeneous integration of logic circuits and complementary metal-oxide-semiconductor (Complementary Metal-Oxide-Semiconductor Transistor, CMOS) image sensors, micro-electromechanical systems (Micro-electromechanical Systems, MEMS), sensors and RF filters . The TSV can also realize the functional integration of photons and light emitting diodes (Light Emitting Diode, LED). [0003] Generally, metallic copper is used for electroplating and deposition of TSVs with a hole depth of more than 30um on the wafer, and then planariz...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): C09G1/02C23F3/04
CPCC09G1/02C23F3/04
Inventor 宋英英王晗笑姜鉴哲张琳
Owner 博力思(天津)电子科技有限公司
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