Integrated trench gate power semiconductor transistor with low characteristic on-resistance

Abstract

The invention provides an integrated trench gate power semiconductor transistor with low characteristic on-resistance. The integrated trench gate power semiconductor transistor comprises a P-type substrate, wherein an N-type epitaxial layer is arranged above the substrate, a dielectric trench is arranged in the epitaxial layer, an N-type heavily doped drain region is arranged on one transverse side of the trench and is located on the surface of the epitaxial layer, a drain metal electrode is connected to the drain region, an N-type heavily-doped source region and a P-type heavily-doped body contact region are arranged on the other transverse side of the trench, a P-type body region is arranged below the source region and the body contact region, a first source electrode metal electrode is connected to the source region and the body contact region, a first insulating medium is filled in the trench and located below the trench, a gate oxide layer, a polycrystalline silicon gate and a second insulating medium are arranged in the trench, the gate oxide layer is located between a gate electrode and the source region, the second insulating medium is located between the gate electrode and the drain region and attached to the inner wall of the trench, the gate electrode is arranged in the trench in a bias mode and is close to the source region, and a polycrystalline silicon field plate is arranged in the first insulating medium and is positioned below the gate electrode.

Description

technical field [0001] The invention mainly relates to the technical field of power semiconductor transistors, in particular to an integrated trench gate power semiconductor transistor with low characteristic on-resistance. Background technique [0002] With the increasing demand for power management integrated circuits in aerospace, ship drive, automotive electronics, consumer electronics, and smart grid applications, in order to improve the integration and efficiency of power integrated circuits and reduce manufacturing costs, it is necessary to integrate high-voltage Metal-oxide-semiconductor field-effect transistors (MOSFETs), digital circuits, and analog circuits are integrated into a single power chip. At the same time, integrated power devices must maintain high currents in the on-state and withstand high voltages in the off-state, so for power For MOSFET devices, the characteristic on-resistance (RON,sp) and breakdown voltage (BV) are the two most important figures o...

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Problems solved by technology

Among them, the lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) is the most commonly used integrated power semiconductor device (see figure 1 ), is compatible with the conventional BCD manufacturing process of integrated circuits, but the length of the drift region between the source and drain of this structure is proportional to the lateral cell size, and a higher BV means a larger chip area and higher feature The on-resistance reduces the efficiency of smart power integrated circuits and limits the improvement of performance; compared with integrated power devices such as LDMOS, discrete power devices represented by vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOS) The device has a vertical structure, and the withstand voltage direction is vertical, so the breakdown voltage of the device has nothing to do with the lateral cell size, so under the same BV, the discrete power device can greatly reduce the lateral cell size, thereby greatly reducing the characteristic on-resistance , but this device structure is not compatible with the conventional BCD process of integrated circuits

see also Figure 9 , this kind of integrated power semiconductor transistor that directly introduces trench structure into LDMOS can expand the one-dimensional withstand voltage of traditional integrated devices to two-dimensional withstand voltage, including two directions of lateral withstand voltage and vertical withstand voltage. The withstand voltage does not occupy the size of the lateral cell. Although the device can reduce the characteristic on-resistance while keeping the breakdown voltage constant, the gate and field plate in the trench adopt a parallel structure, that is, the gate and field plate present The lateral arrangement limits the further reduction of the lateral cell size, and the thickness adjustment of the dielectric layer between the field plate and the drift region is also constrained by the width of the gate itself. In addition, the gate and the field plate in the device trench are directly The electrodes are drawn upward from the surface, which makes the structure more complicated and the manufacturing process difficult

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