Method for manufacturing silicon transistor with high back voltage and low negative resistance

Abstract

The manufacturing method includes cleaning N type polished silicon chip, primary oxidation, a beginning production and diffusing gallium in a base region, primary photoctching and subsequent routine procedures. Before primary photoctching, a film of silicon nitride Si3N4 in thickness 1000A is grew on the SiO2 by using the gas phase deposition method in low pressure. In the step of beginning production and diffusing gallium, the invention uses technical treatments of light concentration adulteration, pushing junction depth and high concentration adulteration in back surface continuously completed in same stove to form P type Ga base region so as to guarantee properties of high voltage and large current of the products. The characteristic of Si3N4 thin film of masking diffused gallium is utilized to prevent Ga diffusion in the procedure of phosphorus diffusion. Thus, the invention improves the amplification performance in small injection and decreases dynatron effect of transistors with Ga base.

Description

(1) Technical field [0001] The invention relates to a manufacturing process of a high back-voltage crystal triode, in particular to a manufacturing method of a high back-voltage low negative resistance silicon transistor. (2) Background technology [0002] In the production of NPN-type silicon mesa high back-voltage transistors, different selections of impurity sources in the P-type base region determine the performance and process flow of the product. Specifically, (1) boron diffusion process, due to the high solid solubility of boron in silicon, the diffusion coefficient is too small, and the impurity cannot form a linear and slowly changing distribution near the PN junction, resulting in a low level of device withstand voltage. (2) Boron-aluminum coating diffusion process, the product has good pressure resistance characteristics, but because the coating is expanded first and then the polishing is expanded, the mechanical polishing causes a large deviation in the width of ...

AI Technical Summary

Problems solved by technology

Specifically, (1) boron diffusion process, due to the high solid solubility of boron in silicon, the diffusion coefficient is too small, and the impurity cannot form a linear slow-change distribution near the PN junction, resulting in low device withstand voltage level

(2) Boron-aluminum coating diffusion process, the product has good pressure resistance characteristics, but because the coating is expanded first and then the polishing is expanded, the mechanical polishing causes a large deviation in the width of the base area, resulting in dispersion of device electrical parameters (especially the current amplification factor) Large, the current characteristics are not ideal, and the process is complicated, the cycle is long, and the cost is large

(3) The closed-tube gallium diffusion process has good device withstand voltage characteristics and good current characteristics, but this process requires difficult vacuum sealing technology, poor process repeatability, and high scrap rate. Diffusion quality, production efficiency, and cost. unsatisfactory

However, in the redistribution process (generally called the secondary oxidation process) in the phosphorus diffusion emission region, due to the extremely large diffusion coefficient of Ga in silicon dioxide (between 1200 and 1250 ° C, D SiO2 / D Si ≈500), the result of segregation leads to the depletion of impurity Ga in the base region near the silicon surface (the micro-region from the base region surface to the silicon body), which causes the degradation of the amplification performance of the device under the condition of small implantation, and then leads to the Ic- Large negative resistance effect on the Vce curve, which is undesirable

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