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Semiconductor device and manufacturing method of the same

A semiconductor and device technology, applied in the field of semiconductor devices and their manufacturing, can solve problems such as unobtainable, unavailable LDD, parasitic resistance, etc., and achieve the effects of improving yield, suppressing short channel effect, and high reliability

Inactive Publication Date: 2006-10-04
SEMICON ENERGY LAB CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the conventional method, although the gate length and the semiconductor film length of the submicron size can be formed by etching, it is impossible to provide an LDD region whose LDD length is suitable for this size.
Submicron TFTs with preferred properties are then not available
[0012] In addition, there is a problem when TFTs are miniaturized, that is, the influence of parasitic resistance due to the generation of LDD regions

Method used

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  • Semiconductor device and manufacturing method of the same
  • Semiconductor device and manufacturing method of the same
  • Semiconductor device and manufacturing method of the same

Examples

Experimental program
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Embodiment approach 1

[0073] Refer to the following Figure 1A - 1D, 2A-2H, 3A-3D, 4A-4C to describe the semiconductor device manufacturing method according to Embodiment 1. The TFT used in the semiconductor device of this embodiment has a Lov region and an Loff region as LDD regions.

[0074] First, base insulating film 12 is formed on substrate 11 to a thickness of 100-300 nm. As the substrate 11, an insulating substrate such as a glass substrate, a quartz substrate, a plastic substrate, or a ceramic substrate; a metal substrate; a semiconductor substrate; and the like can be used.

[0075] Silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide containing nitrogen (SiOxNy) (x > y) (also called silicon oxynitride), or silicon nitride containing oxygen (SiNxOy) (x >y) (also referred to as silicon oxynitride) or a single-layer structure of an insulating film containing oxygen or nitrogen, or a stacked layer structure thereof, to form the base insulating film 12 . Specifically, when impuritie...

Embodiment approach 2

[0121] In this embodiment, a method of manufacturing a semiconductor device having only the Lov region is described with reference to FIGS. 5A to 5F. Also, in this embodiment, the same reference numerals are used for the same parts as in Embodiment 1, and detailed explanation thereof is omitted.

[0122] In this embodiment, a TFT is manufactured through the same steps as in Embodiment 1 up to FIG. 2A. Subsequently, using the first electrode 20 as a mask, doping with impurity ions 32 is performed to form high-concentration impurity regions 52a and 52b (FIG. 5A). In addition, the doping of impurity ions 32 for forming a high-concentration impurity region and the doping of impurity ions 27 for forming a low-concentration impurity region may be performed in reverse order; 27 doping, so as to obtain the state of Figure 5A. Alternatively, the doping of the impurity ions 27 may be omitted and only the doping of the impurity ions 32 may be performed. When doping of impurity ions 32...

Embodiment 3

[0132] In this embodiment, a method of manufacturing a semiconductor device having only the Loff region is described with reference to FIGS. 6A to 6F. Also, in this embodiment, the same reference numerals are used for the same parts as in Embodiments 1 and 2, and detailed explanation thereof is omitted.

[0133] Up to FIG. 5A , the same steps as Embodiment 2 are performed, and low-concentration impurity regions 24 a and 24 b , high-concentration impurity regions 52 a and 52 b , and channel formation region 26 are formed in island-shaped semiconductor film 13 . Then, using the second gate electrode 22 as a mask, dry etching is performed to etch the first gate electrode and the gate insulating film 14 to have the same width as the gate length of the second gate electrode. With this etching, the third gate electrode 62 and the gate insulating film 61 are formed, and part of the island-like semiconductor film 13 is exposed (FIG. 6A).

[0134] Subsequently, an insulating film is d...

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Abstract

It is an objective of the present invention to manufacture a minute TFT having an LDD region through process with the reduced manufacturing steps, and form a TFT having a structure suitable for each circuit. It is also an objective of the present invention to secure an ON current even in a TFT having an LDD region. A hat-shaped gate electrode is formed by forming a two-layer gate electrode in which the gate length of a lower layer of the gate electrode is longer than that of an upper layer of the gate electrode. The hat-shaped gate electrode is formed by etching only the upper layer of the gate electrode by making the use of the resist recess width. In addition, silicide is formed in a contact portion of a wiring and a semiconductor film to lower contact resistance.

Description

technical field [0001] The present invention relates to semiconductor devices forming various circuits and methods of manufacturing the same. Background technique [0002] A conventional thin film transistor (hereinafter referred to as TFT) is made of an amorphous semiconductor film; thus it is almost impossible to obtain a field effect mobility of 10 cm 2 / Vsec or above TFT. However, since TFTs made of crystalline semiconductor films have appeared, TFTs with high field-effect mobility can be obtained. [0003] Since TFTs made of crystalline semiconductor films have high field-effect mobility, it is possible to simultaneously form various functional circuits using TFTs on the same substrate. For example, in a display device, a driver IC or the like is mounted on a display portion so as to have a driving circuit in advance. On the other hand, with TFTs made of a crystalline semiconductor film, a display portion and a drive circuit composed of a shift register circuit, a le...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/423H01L29/786H01L21/336H01L21/28
CPCH01L29/66757H01L29/4908H01L29/42384H01L27/1214H01L29/78621H01L29/458H01L2029/7863H01L27/127H01L27/1266H01L27/124H01L21/18
Inventor 磯部敦生德永肇山口真弓
Owner SEMICON ENERGY LAB CO LTD