Deaprom having amorphous silicon carbide gate insulator

Abstract

A floating gate transistor has a reduced barrier energy at an interface with an adjacent amorphous silicon carbide (a-SiC) gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] The present application is a continuation of U.S. Ser. No. 09 / 134,713, filed on Aug. 14, 1998; which is a divisional of U.S. Ser. No. 08 / 902,843, filed Jul. 29, 1997, now abandoned; each of which is incorporated herein by reference in its entirety. [0002] This application is related to the following co-pending, commonly assigned U.S. patent applications: “MEMORY DEVICE,” Ser. No. 08 / 902,133; “DEAPROM AND TRANSISTOR WITH GALLIUM NITRIDE OR GALLIUM ALUMIUM NITRIDE GATE,” Ser. No. 08 / 902,098, now issued as U.S. Pat. No. 6,031,263; “CARBURIZED SILICON GATE INSULATORS FOR INTEGRATED CIRCUITS,” Ser. No. 08 / 903,453; “TRANSISTOR WITH VARIABLE ELECTRON AFFINITY GATE AND METHODS OF FABRICATION AND USE,” Ser. No. 08 / 903,452, now abandoned; “SILICON CARBIDE GATE TRANSISTOR AND FABRICATION PROCESS,” Ser. No. 08 / 903,486, now issued as U.S. Pat. No. 6,936,849; and “TRANSISTOR WITH SILICON OXYCARBIDE GATE AND METHODS OF FABRICATION AND USE,” Ser. No. 0...

AI Technical Summary

Benefits of technology

[0011] Another aspect of the present invention provides a method of using a floating gate transistor having a reduced barrier energy between a floating gate electrode and an adjacent a-SiC insulator. Data is stored by changing the charge of the floating gate. Data is refreshed based on a data charge retention time established by the barrier energy. Data is read by detecting a conductance between a source and a drain. The large transconductance gain of the memory cell of the present invention provides a more easily detected signal and reduces the required data storage capacitance value and memory cell size when compared to a conventional dynamic random access memory (DRAM) cell.

[0012] The present invention also includes a method of forming a floating gate transistor. Source and drain regions are formed. An a-SiC gate insulator is formed. A floating gate is formed, such that the floating gate is isolated from conductors and semiconductors. The a-SiC gate insulator provides a relatively short data charge retention time, but advantageously provides a shorter write/programming and erase times, making operation of the present memory speed competitive with a DRAM.

[0013] The present invention also includes a memory device that is capable of providing short programming and erase times, low programming and erase voltages, and lower electric fields in the memory cell for improved reliability. The memory device includes a refresh circuit and a plurality of memory cells. Each memory cell includes a transistor. Each transistor includes a source region, a drain region, a channel region between the source and drain regions, and a floating gate that is separated from the channel region by an a-SiC gate insulator. The transistor also includes a control gate located adjacent to the floating gate and separated therefrom by an intergate dielectric. The memory device includes flash electrically erasable and programmable read only memory (EEPROM), dynamic random access memory (DRAM), and dynamically electrically alterable and programmable read only memory (DEAPROM) embodiments.

[0014] The memory cell of the present invention provides a reduced barrier energy, large transconductance gain, an easily detected signal, and r

Problems solved by technology

Such effects can result in erroneous data.

However, formation of stacked capacitors typically requires complicated process steps.

Stacked capacitors also typically increase topographical features of the integrated circuit die, making subsequent lithography and processing, such as for interconnection formation, more difficult.

Alternatively, storage capacitors can be formed in deep trenches in the semiconductor substrate, but such trench storage capacitors also require additional process complexity.

However, the relatively large electron affinity of the polysilicon floating gate presents a

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