Semiconductor Device

Abstract

A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]The present application claims priority from Japanese Patent Application No. JP 2005-378490 filed on Dec. 28, 2005, the content of which is hereby incorporated by reference into this application.TECHNICAL FIELD OF THE INVENTION[0002]The present invention relates to a semiconductor device, and particularly to a technique effectively applied to a semiconductor device having a semiconductor memory with a large storage capacity, and required for high-speed read operation.BACKGROUND OF THE INVENTION[0003]According to speed-up of a CPU, a demand for improvement of an operation frequency of a semiconductor memory is increasing year after year. In a conventional synchronous dynamic random access memory (SDRAM), speed-up has been achieved by raising an integration degree based upon miniaturization. In a double data rate synchronous dynamic random access memory (DDR SDRAM) which is currently mainstream, a data transfer rate has been improved by util...

AI Technical Summary

Benefits of technology

[0014]A semiconductor device according to the present invention comprises a memory cell array represented by DRAM array, input/output lines having a hierarchical structure, a sub-amplifier, a main amplifier, and a timing controller. The sub-amplifier amplifies faint signals read to lower input/output lines via the sense amplifier in the memory array. The sub-amplifier comprises, for example, a plurality of current sources having different conductance to each other and the current sources are activated independently by a plurality of read enable signals. The main amplifier amplifies faint voltage signal read to the upper input/output line via the sub-amplifier. The timing controller detects the number of cycles of burst read operation and generates a column select signal and a plurality of read enable signals with a timing according to the number of cycles. In a cycle of burst read operation just after bank activation, the timing controller activates a column signal and a first read enable signal with a timing later than that of subsequent cycles. With the first read enable signal, a current source having large conductance is activated and driving ability of the sub-amplifier is set to be high, thereby shortening data transfer time of the input/output lines (high speed mode). Therefore, in the memory array, it is possible to expand a read operation margin to realize read operation with high sp

Problems solved by technology

The first problem lies in that it is predicted that time required for reading stored data increases due to an RC delay (here, R represents wiring resistance and C represents load capacitance). FIG. 2 shows a diagram showing an example of an operation timing diagram in a read operation of a DDR SDRAM.

However, in consideration of the RC delay according to chip area of a DDR SDRAM of Gigabit class, since a row select operation time increases as shown in FIG. 3, a word line enable timing may delay by a time TRD0

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