Method for manufacturing longitudinal double-grid metal-oxide-semiconductor element

A gate metal and oxide technology, which is applied in the field of manufacturing vertical double-gate MOS devices based on silicon-on-insulator materials, can solve the problems of small overlapping area of ​​modulation area and light field, and the modulation efficiency needs to be improved, so as to achieve the effect of reducing the complexity of process manufacturing

Inactive Publication Date: 2009-12-23
INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The MOS structure avoids the influence of the carrier recombination process on the modulation rate of the device, but the overlapping area of ​​the modulation area and the light field is small, and the modulation efficiency needs to be improved.

Method used

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  • Method for manufacturing longitudinal double-grid metal-oxide-semiconductor element
  • Method for manufacturing longitudinal double-grid metal-oxide-semiconductor element
  • Method for manufacturing longitudinal double-grid metal-oxide-semiconductor element

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Embodiment

[0056] Such as figure 2 As shown, figure 2 In order to manufacture a process flow chart of a vertical dual-gate MOS device according to an embodiment of the present invention, the method specifically includes the following steps:

[0057] First, the SOI substrate is cleaned. Such as figure 2 As shown in middle figure a, figure a is a schematic diagram of the structure of the SOI substrate used in the present invention.

[0058] Secondly, ordinary photolithography is performed on the cleaned SOI substrate. It is assumed that the top silicon of the SOI substrate itself is P-type low-doped (if the top silicon concentration and type do not meet the requirements, a large-area ion implantation can be used to obtain a rational concentration). Use photoresist as a mask to perform shallow etching of silicon and ion implantation to form a highly doped N region, which is used as an ohmic contact electrode at the end. The purpose of shallow etching silicon is to leave a mark for the next e...

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Abstract

The invention discloses a method for manufacturing a vertical double-gate MOS device. The method includes: A. forming an N-P-N structure by ion implantation technology on the top silicon surface of an SOI substrate, wherein the N region is highly doped and the P region is low doped; B. Using electron beam exposure and ICP etching methods to form a vertical deep groove at the interface between the N region and the P region of the formed N-P-N structure; C. Using thermal oxidation technology to form a layer of oxidation on the top silicon surface forming the vertical deep groove Silicon; D. Using low-pressure chemical vapor deposition technology combined with tetraethyl orthosilicate TEOS source to fill the vertical deep groove with silicon oxide; E. Perform photolithography on the surface of the filled silicon oxide, and corrode the silicon oxide to expose the N region and the P region ; F, evaporating metal on the surface of the exposed N region and P region, and forming electrodes by photolithography and etching. The invention realizes the high-speed transmission of information in the optical communication and inside the chip system.

Description

Technical field [0001] The invention relates to the technical field of vertical dual-gate metal-oxide-semiconductor (MOS) devices in semiconductor devices, and in particular to a method for manufacturing vertical dual-gate MOS devices based on silicon-on-insulator (SOI) materials. Background technique [0002] In recent years, with the rapid development of silicon-on-insulator-compensated metal oxide semiconductor (SOI CMOS) technology and SOI optical waveguide device research, people have continuously turned their attention to the multi-functional integration of optoelectronic devices based on SOI in a chip. [0003] SOI technology has the unparalleled superiority of bulk silicon technology. CMOS devices made on SOI materials have the advantages of low power consumption, strong anti-interference ability, high integration, high speed, simple process, and strong anti-radiation ability. As the thickness of the SOI top silicon film is reduced to less than the width of the device dep...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/28
Inventor 屠晓光陈少武
Owner INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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