Preparation of silicon nanowire array

Abstract

The invention relates to a method for preparing silicon nanowires, belonging to the nanophase material preparation technical field. The method comprises the following steps that: a silicon chip is washed and shaken by acetone and alcohol and is processed by an acid cleaning liquid and a No.1 standard cleaning solution; a silicon dioxide spheres solution with a weight percentage density between 0.02 and 2.0 percent is added on the silicon chip surface which is washed off in the step one drop by drop by a micro pipette, the processed silicon chip is placed in air to air naturally; the silicon chip with silicon dioxide sphere arrays is annealed for one to three hours at a temperature of between 900 and 1000 DEG C; afterwards, the silicon chip is put into a diluent hydrofluoric acid solution to be eroded for 2 to 20 minutes so that the diameters of the spheres become small; an Ag film with a thickness between 20 and 80nm is deposited on the silicon chip surface by the plating technique or the vacuum evaporating technique; and a sample deposited with the Ag film is dipped into the hydrofluoric acid and hydrogen peroxide etching solution (or ferric nitrate) to be eroded for 4 to 100 minutes. The preparation method can rapidly prepare a large area of silicon nanowire arrays, thereby being suitable for the large-scale industrial production.

Description

technical field [0001] The invention relates to a method for preparing silicon nanowires, which belongs to the technical field of nanomaterials. Background technique [0002] One-dimensional semiconductor nanomaterials have broad application prospects in future mesoscopic and nano-optoelectronic devices due to their unique structures and physical properties. Due to the important position of silicon materials in the traditional microelectronics industry, the research of one-dimensional silicon nanowires has received great attention. The current nano-silicon wire preparation methods mainly include chemical vapor deposition and oxide-assisted growth techniques. Due to the limitations of the growth mechanism, these methods usually require relatively high temperatures and some complicated equipment, resulting in high production costs. For example, the silicon wire growth temperature in patent 00117242.5 is as high as 1600-2000°C [refer to: Chinese patent 00117242.5, publication...

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Problems solved by technology

Although this technique can be applied to silicon substrates with different doping types, concentrations and orientations, and can control the length and crystallographic orientation of nanowires, it is difficult to obtain silicon nanowires with uniform diameter and orderly arrangement.

Our research group recently used polystyrene nanosphere template technology to prepare silicon nanowires with uniform diameter and orderly arrangement, but this technology needs to use reactive ion etching (RIE), which seriously reduces the production efficiency and cost of silicon nanowires. substantial improvement

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