Method for manufacturing transistor by using silicon single crystal slices

Abstract

The invention discloses a method for manufacturing a transistor by using silicon single crystal slices, which comprises the steps of: 1) selecting two light-doped polished silicon slices, wherein thefront surfaces thereof are the polished surfaces; 2) conducting N+ or P+ pre-expansion on each silicon slice and then arranging an oxide layer on the front surface of the pre-expanded polished siliconslice; 3) causing the front surfaces of the two polished silicon slices with the oxide layers to face to each other for bonding at room temperature, and putting the obtained bonded silicon slice group into a high-temperature furnace for high-temperature processing; 4) conducting mechanical grinding and polishing on the two surfaces of the obtained silicon slice group; 5) manufacturing a transistor chip on the two surfaces of the silicon slice group respectively; 6) putting the silicon slice group obtained in the Step 5) into an HF solution to separate the silicon slices; and 7) metallizing the surfaces of the silicon slices without the transistor chip, and then removing optical resist, scribing and packaging, thus obtaining the transistor. The method for manufacturing the transistor by using silicon single crystal slices can guarantee the performance of the transistor.

Description

technical field [0001] The invention relates to a method for manufacturing a transistor with a thin single crystal silicon wafer, mainly a method for manufacturing a lightly doped (top layer of the silicon wafer) / heavily doped (bottom layer of the silicon wafer) structure silicon substrate. Background technique [0002] There are usually two methods to produce silicon wafers with N- / N+, P / N+, N / P+, and P / P+ structures: the first method is to epitaxially layer a layer of lightly doped silicon on the surface of heavily doped silicon wafers; the second method is to use Lightly doped silicon wafers are thermally diffused in a diffusion furnace to form heavy doping on the surface, and then one side of the silicon wafers is ground and polished to achieve the above structure. Method 1, that is, the silicon wafer with the above structure made by the epitaxial method is of good quality, but the processing cost is high, and the equipment cost of the epitaxial furnace used is also high...

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Problems solved by technology

But this method has the following disadvantages: 1. Due to the bonding with glass powder, there will inevitably be many bubbles at the bonding interface. The existence of bubbles will cause a large amount of stress between the two silicon wafers. In the subsequent device process , the stress will induce crystal defects

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