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Method for producing novel substrate, epitaxial wafer and semiconductor device

A production method and technology of epitaxial wafers, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of reducing the resistance uniformity of the epitaxial layer, the value of resistivity uniformity is difficult to reduce, and the resistivity uniformity is low , to achieve a steep SRP curve, reduce subsequent production costs, and improve product quality

Inactive Publication Date: 2012-04-11
SHANGHAI JINGMENG SILICON CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] Currently, the acceptable range for resistivity uniformity of epitaxial wafers is less than 5%
However, the epitaxial wafers in the prior art have the lowest resistivity uniformity of only 2.5%. According to the existing technology, it is difficult to reduce the resistivity uniformity value.
[0009] The interdiffusion of impurities in the substrate and impurities in the epitaxial layer reduces the resistance uniformity of the epitaxial layer

Method used

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  • Method for producing novel substrate, epitaxial wafer and semiconductor device
  • Method for producing novel substrate, epitaxial wafer and semiconductor device
  • Method for producing novel substrate, epitaxial wafer and semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1-4

[0034] Such as figure 2 As shown, the new type of substrate includes a substrate body 1 with a single crystal silicon layer 2 on the surface of the substrate body 1. The thickness of the single crystal silicon layer 2 is 2-5 μm. The specific thickness can be determined according to the overall thickness of the epitaxial wafer and the thickness of the substrate body. The higher the substrate thickness, the thicker the single crystal silicon layer. In subsequent production, an epitaxial layer is grown on the surface of the single crystal silicon layer 2.

[0035] The substrate body 1 may be N-type, that is, doped with arsenic, phosphorus, or antimony; the substrate body 1 may also be P-type, that is, doped with boron.

[0036] Embodiments 1-4 are all heavily arsenic-doped substrate bodies. In Embodiments 1-4, 2 μm, 2.6 μm, 3.5 μm, and 4.8 μm single crystal silicon layers are respectively arranged between the substrate body and the epitaxial layer.

[0037] In Examples 1-4, the mono...

Embodiment 5-8

[0039] image 3 It is a schematic diagram of the structure of the epitaxial wafer in Examples 5-8. Examples 5-8 use the substrates in Examples 1-4, respectively. Such as image 3 As shown, an epitaxial layer 3 is formed on the surface of the single crystal silicon layer 2. The monocrystalline silicon layer 2 is located between the substrate body 1 and the epitaxial layer 3.

[0040] In Comparative Examples 1-4, the substrate body is a heavily arsenic-doped body, and no single crystal silicon layer is provided between the substrate body and the epitaxial layer.

[0041] The comparison data of the resistance uniformity of the epitaxial layer of Examples 5-8 and Comparative Examples 1-4 are shown in Table 1-4. In each group of comparisons, two substrate bodies produced in the same batch are selected, one is provided with a monocrystalline silicon layer and then the epitaxial layer is grown; the other is directly grown with the epitaxial layer. The epitaxial layer growth process is ...

Embodiment 9

[0053] Two heavily phosphorus-doped substrate bodies produced in the same batch were selected, one was used in Example 9. The epitaxial layer 3 was grown after the monocrystalline silicon layer 2 was grown on the surface of the substrate body 1; the other was used in Comparative Example 5. The epitaxial layer is directly grown on the surface of the substrate body. The single crystal silicon layer 2 in Embodiment 9 is produced by reacting trichlorosilane with hydrogen. The reaction temperature is 960°C, and the hydrogen flow rate is 140 slm / s. The single crystal silicon formed by the reaction is deposited on the surface of the substrate body 1 to form a single crystal silicon layer 2. The single crystal silicon layer 2 has a thickness of 4 μm.

[0054] In Comparative Example 5, no single crystal silicon layer is provided between the substrate body and the epitaxial layer.

[0055] The epitaxial layer growth process in Example 9 and Comparative Example 5 are the same.

[0056] The ...

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Abstract

The invention discloses a method for producing a novel substrate. The novel substrate comprises a substrate body and is characterized in that: the surface of the substrate body is provided with a monocrystalline silicon layer; and the monocrystalline silicon layer is formed by depositing monocrystalline silicon which is generated by reacting trichlorosilane and hydrogen at the temperature of between 900 and 1,050 DEG C on the surface of the substrate body. The resistance uniformity of the epitaxial wafer which is produced by using the novel substrate is less than 1.5 percent. Compared with the epitaxial wafer which is not produced by using the novel substrate, the epitaxial wafer has the advantages that the resistance uniformity value of the epitaxial wafer can be reduced by 1 percent. By using the novel substrate, the subsequent production cost can be reduced and product quality can be improved.

Description

Technical field [0001] The invention relates to a new type of substrate production method, epitaxial wafer and semiconductor device. Background technique [0002] For semiconductor devices, the epitaxial layer needs to have a perfect crystal structure, and there are certain requirements for the thickness, conductivity type, resistivity, and uniformity of the resistance of the epitaxial layer. The resistivity of semiconductors generally changes with changes in factors such as temperature, doping concentration, magnetic field strength, and light intensity. [0003] The combination of epitaxial layer and substrate and product specifications are determined by subsequent product applications. Circuits and electronic components need to be fabricated on epitaxial wafers. For different applications, such as MOS type, PMOS, NMOS, CMOS, and bipolar type, saturated type and unsaturated type. With the development trend of integrated circuit design towards light, thin, short, small and power ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/205
Inventor 顾昱钟旻远林志鑫陈斌
Owner SHANGHAI JINGMENG SILICON CORP
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