30results about How to "Improve resistivity uniformity" patented technology

The invention discloses a method for improving the uniformity of axial resistivity of czochralski silicon. The method comprises the steps as follows: (1) melting a polycrystalline silicon raw material and a solid doping agent in an argon atmosphere to obtain stable molten silicon; (2) introducing seed crystals into the stable molten silicon, and conducting constant diameter growth on the crystals after necking and shouldering processes; and (3) during the constant diameter growth period, adding dopant gas with the conductive type opposite to that of the solid doping agent until the growth of the czochralski silicon is fulfilled. According to the method, the type and the usage amount of the dopant gas are convenient to control, various required impurity concentration distributions can be obtained, the utilization rate of the czochralski silicon is increased, and the uniformity of the resistivity of the czochralski silicon is remarkably improved.

An intermediate transfer medium including a layer which includes an acidic carbon black including volatile components of from 3.5 to 8.0% by weight; at least one of a water soluble resin having a weight average molecular weight of from 3,000 to 30,000, and a resin dispersant having a weight average molecular weight of from 3,000 to 300,000 which is selected from the group consisting of polyamide acids, polyimides, and block copolymer including a unit containing at least one of a polyamide acid and a polyimide; and a binder resin, wherein a weight ratio (CB/R) of the carbon black (CB) to the at least one (R) of the water soluble resin and the resin dispersant is from 3/1 to 10/1. A film forming liquid for use in preparing the layer, and an image forming apparatus using the intermediate transfer medium are also provided.

A thin film transistor substrate includes a base substrate, an active pattern, a gate insulation pattern and a gate electrode. The active pattern is disposed on the base substrate. The active pattern includes a source electrode, a drain electrode, and a channel disposed between the source electrode and the drain electrode. The gate insulation pattern and the gate electrode overlap with the channel. The gate insulation pattern is disposed between the channel and the gate electrode. The source electrode and the drain electrode each include a fluorine deposition layer.

The invention discloses an epitaxial wafer substrate capable of reducing auto-doping during epitaxy. The epitaxial wafer substrate comprises a substrate body, and is characterized in that: the back surface of the substrate body is provided with a silicon dioxide layer. When an epitaxial layer generated by using the epitaxial wafer substrate capable of reducing the auto-doping during epitaxy is used, the resistivity uniformity numerical value can be less than 1.5 percent. Compared with an epitaxial layer which is generated by not using the epitaxial wafer substrate capable of reducing the auto-doping during epitaxy, the epitaxial layer which is generated by using the epitaxial wafer substrate capable of reducing the auto-doping during epitaxy has higher epitaxial layer resistance uniformity. By using the epitaxial wafer substrate capable of reducing the auto-doping during epitaxy, the follow-up production cost can be reduced, and the product quality can be improved.

The invention discloses a control method for an external extension transition section on a heavy doping arsenic underlay, which adopts chemical vapor deposition technology to grow light doping thin silicon extension layer at two times on a n-type heavy doping arsenic silicon underlay. After the growing of a first own extension layer, reduce the temperature to 870 to 930 DEG C. and take it out. During the process, remove the memory effect by putting in a HCI erosion base. After the completion of erosion, place the piece in furnace under the temperature of 870 to 930 DEG C. and then grow the residual extension layer. By checking and comparing the extension layer made with ordinary method and the method in the invention via an extension resistance analyzer, it is proved that the extension layer made of the method in the invention has steepy transition section and resistance of the extension layer has excellent evenness.

The invention discloses a P-type silicon mother alloy production method, which comprises the steps of selecting a corresponding silicon material according to the boron element concentration and the phosphorus element concentration in target silicon mother alloy; calculating the amount of boron material and phosphorus material which are need to be added according to the boron element concentration and the phosphorus element concentration of the silicon material, and the boron element concentration and the phosphorus element concentration in the target silicon mother alloy; putting the silicon material, the amount of boron material and phosphorus material simultaneously into a single crystal furnace, and pulling to prepare the P-type silicon mother alloy by using a Czochralski method. The P-type silicon mother alloy production method can improve the uniformity of the P-type mother alloy resistivity, reduce the amount of boron dopants and reduce the resistivity levels, thereby reducing the production cost.

There is provided an electrode paste composition, an electrode for an electronic device using the same, and a method of manufacturing the same. The electrode for an electronic device includes: a substrate; a thin film layer formed on the substrate, the thin film layer including reduced graphene oxide (rGO); and an oxide layer formed between the substrate and the thin film layer. The electrode for an electronic device may have excellent uniform resistivity and electrical conductivity since the electrode is formed by coating the substrate with a solution containing graphene oxide having superior dispersibility and reducing the graphene oxide.

The invention discloses a substrate. The substrate comprises a substrate body and is characterized in that a first silicon dioxide layer is arranged at the back side of the substrate body; a polycrystalline silicon layer is arranged on the surface of the first silicon dioxide layer; and a second polycrystalline silicon layer is arranged on the surface of the polycrystalline layer. The invention has another advantage of being capable of improving the flatness of an epitaxial wafer and increasing the resistivity uniformity of an epitaxial layer.

The invention discloses a manufacturing method of a silicon epitaxial wafer for an 8-inch VDMOS power tube, which comprises the steps of (1) selecting an As-doped substrate, wherein the resistivity ofthe substrate is less than or equal to 0.004 omega.cm; (2) growing a first epitaxial layer, wherein the first epitaxial layer grows on the surface of the substrate at the growth temperature of 1040-1080 DEG C and the growth rate of less than or equal to 1.5[mu]m/min, and purging the cavity with hydrogen after the growth of the first epitaxial layer is completed; and (3) and growing a second epitaxial layer, wherein second epitaxial layer grows on the surface of the first epitaxial layer at the growth temperature of 1040-1060 DEG C and the growth rate of 2-3[mu]m/min. According to the invention, the proper substrate is selected, the device and epitaxial requirements are met, the resistivity uniformity of the epitaxial layer is effectively improved, the deviation between the edge and the central region transition region is reduced, and the yield of the die is improved.

An apparatus and method for recharge raw material in the crystal growth. Use a feed tube to recharge raw material in a crucible. Cover the lower end of the tube with a plate. The plate is made of the same raw material as the charge in the crucible. Load the raw material in the tube, and then lower the tube into the melt in crucible. When the plate is melted, the raw material in the tube is droped into the crucible. It can be recharged using the feed tube after pulling a ingot, sequentially multiple ingots can be grown by using one crucible. In this apparatus and methods, there are not limited for the shape and size of the raw material, and increase the quantity of the raw material with one time. This apparatus and method can improve productivity, product quality and yield. Lowering material consumption, energy and cost.

The invention discloses a method for producing a novel substrate. The novel substrate comprises a substrate body and is characterized in that: the surface of the substrate body is provided with a monocrystalline silicon layer; and the monocrystalline silicon layer is formed by depositing monocrystalline silicon which is generated by reacting trichlorosilane and hydrogen at the temperature of between 900 and 1,050 DEG C on the surface of the substrate body. The resistance uniformity of the epitaxial wafer which is produced by using the novel substrate is less than 1.5 percent. Compared with the epitaxial wafer which is not produced by using the novel substrate, the epitaxial wafer has the advantages that the resistance uniformity value of the epitaxial wafer can be reduced by 1 percent. By using the novel substrate, the subsequent production cost can be reduced and product quality can be improved.

The invention discloses a manufacturing and processing method for improving seed crystal defects of a germanium single crystal, and belongs to the field of crystal processing. The manufacturing and processing method for improving the seed crystal defects of the germanium single crystal comprises the following steps: step 1, drawing a single crystal with a proper size according to the size of a seed crystal chuck and the required size; step 2, necking a section at a taper part needing to be processed in the later period through more detailed manual control; and step 3, adopting slow shouldering, wherein the shouldering speed ranges from 10 mm/h to 15 mm/h, and the shouldering angle is larger than 45 degrees. The resistivity uniformity of the germanium seed crystal is greatly improved, the dislocation density and internal defects of the seed crystal are reduced, and a high-quality seed crystal raw material grows.

The invention discloses a novel substrate, which comprises a substrate body, and the novel substrate is characterized in that a monocrystalline silicon layer is arranged on the surface of the substrate body. The resistivity uniformity of an epitaxial layer produced with the novel substrate in the invention can be less than 1.5 percent. Compared with the resistivity uniformity value of an epitaxial layer which is not produced with the novel substrate in the invention, the resistivity uniformity value of the epitaxial layer in the invention can be decreased by one percent. By means of using the novel substrate in the invention, the subsequent production cost can be reduced, and the quality of products can be increased.

The invention provides a coil structure for improving the zone-melting radial resistivity uniformity. The coil structure comprises a coil main body, a cooling water pipeline, a main seam, a plurality of sub seams and a plurality of transverse seams, wherein the coil main body is a flat plate coil; the upper surface of the coil main body is sunken into the inside of the coil into a centrosymmetric step structure; a coil hole is formed in the geometric center part of the coil main body; the cooling water pipeline is positioned inside a step at the outermost layer of the coil main body; the main seam is arranged on the coil main body in the radial direction and penetrates through the upper surface and the lower surface of the coil main body; the plurality of sub seams are arranged on the step surface at the innermost layer of the coil main body and penetrate through the upper surface and the lower surface of the step surface; the transverse seams are partially or all arranged on the sub seams; the transverse seams are perpendicular to the respective sub seam. The coil structure for improving the zone-melting radial resistivity uniformity has the advantage that due to the adaption of the technical scheme, the zone-melting silicon single-crystal radial resistivity uniformity can be simultaneously improved.

The invention provides a tray of semiconductor processing equipment and the semiconductor processing equipment. The tray of the semiconductor processing equipment comprises a tray body and a supporting part, an accommodating groove for accommodating a wafer is formed in the tray body, the accommodating groove comprises a convex part positioned on the bottom surface of the accommodating groove, theupper surface of the convex part is an arc surface, and the distance between a point on the arc surface and the bottom surface of the accommodating groove is gradually reduced from the center of thearc surface to the edge so as to reduce the temperature difference between the center of the tray and the edge of the tray; the supporting part is arranged on the tray body and surrounds the peripheryof the arc surface, the supporting part is used for supporting the wafer, and a gap is formed between the wafer and the arc surface, so that the heat conduction efficiency of the tray to the edge ofthe wafer is reduced. According to the tray of the semiconductor processing equipment and the semiconductor processing equipment provided by the invention, the temperature uniformity of the wafer in the semiconductor technological process can be improved, so that the resistivity uniformity of an epitaxial layer is improved.

The invention discloses preparation methods of high-quality semi-insulating silicon carbide single crystal doped with a small amount of vanadium and a high-quality semi-insulating silicon carbide single crystal substrate doped with a small amount of vanadium, and belongs to the field of semiconductor materials. The preparation method of the semi-insulating silicon carbide single crystal comprisesthe steps: removing impurities of a thermal field device, mixing materials, performing crystal growth and conducting annealing treatment. The preparation method of the semi-insulating silicon carbidesingle crystal has low technical cost and capital cost, and the resistivity of the prepared silicon carbide single crystal depends on residual shallow energy level impurities and a small amount of vanadium element; since lattice positions are occupied by the impurities, the impurities have high thermal stability, it means that the crystal can have highly stable resistivity; and since the silicon carbide single crystal substrate prepared from the silicon carbide single crystal has high resistivity uniformity and low stress, so that the silicon carbide single crystal substrate has excellent surface quality, and the stability and consistency of the substrate quality in the subsequent epitaxial process are ensured.

The invention relates to a preparation method for a doped float zone silicon crystal. The method comprises that: (1) cone grinding, corrosion, cleaning and drying are performed on a polysilicon material; (2) the polysilicon material is fixed in a cavity of a magnetron sputtering apparatus, a phosphorus-silicon-doped target is arranged, vacuumizing is performed to achieve 5*10<-3> Pa, argon gas is introduced to achieve the pressure in the cavity of 1 Pa, a high voltage of 500 Kv is applied between the two electrodes, argon ions produced through ionization continuously bombard the target, the phosphorus atoms and the silicon atoms in the target obtain energy, sputter, and deposit on the surface of the polysilicon to form a layer of a uniform and compact phosphorus/silicon film, the sputtering is performed for 30-90 min and then is stopped, the sputtering chamber is opened to rotate the polysilicon 180 DEG, the steps are repeated, and the sputtering is continuously performed for the same time; and (3) the polysilicon material is taken out and placed into a float zone silicon crystal furnace, the seed crystal and the polysilicon are centered, steps of vacuumizing, argon gas introduction, preheating, fusion splicing, narrow neck shrinking and crystal diameter achieving are sequentially performed until the equal diameter is maintained, and the ending step is performed. The preparation method has characteristics of low-cost, high production efficiency and no toxicity and harm, wherein the uniformities of the radial resistivity and the axial resistivity are good.

The invention discloses high-quality semi-insulating silicon carbide single crystal doped with a small amount of vanadium and a silicon carbide single crystal substrate, and belongs to the field of semiconductor materials. The semi-insulating silicon carbide single crystal comprises shallow energy level impurities, a low-concentration deep energy level dopant and a very small amount of intrinsic point defects, wherein the shallow energy level impurities are compensated by the deep energy level dopant and the intrinsic point defects together, the concentration of the deep energy level dopant issmaller than that of the deep energy level dopant in the doped semi-insulating silicon carbide single crystal, and the concentration of the intrinsic point defects is the primary concentration of theintrinsic point defects in the silicon carbide single crystal at room temperature; and the stability of the electrical properties of the silicon carbide single crystal is not affected by the concentration of the intrinsic point defects. The semi-insulating silicon carbide single crystal has highly stable resistivity and high resistivity uniformity, and the silicon carbide single crystal substrateprepared from the silicon carbide single crystal has high resistivity uniformity and low stress, so that the silicon carbide single crystal substrate has excellent surface quality, and the stabilityand consistency of subsequent epitaxial quality are ensured.