Method for manufacturing high-voltage semiconductor device

Abstract

The embodiment discloses a method for manufacturing a high-voltage semiconductor device, which comprises the steps as follows: a substrate is provided, an etching barrier layer material on an STI shallow trench corner is partially removed in the horizontal direction; a body layer material on the STI shallow trench corner is removed to enable the sharp corner of the STI shallow trench to become round and smooth; an STI shallow trench isolation region, and a well region and a drift region of the high-voltage semiconductor device are formed; and a gate dielectric layer is formed on the substrate surface including the STI shallow trench isolation region as well as the well region and the drift region of the high-voltage semiconductor device. According to the embodiment of the invention, the body layer material on the STI shallow trench corner is removed to enable the sharp corner of the STI shallow trench to become round and smooth, and the stress on the STI shallow trench corner is reduced, so that a follow-up formed liner oxidation layer is distributed more evenly on the STI shallow trench corner, furthermore the phenomenon of thin gate dielectric layer on the STI shallow trench isolation region corner is improved, and the performance of the device is remarkably improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, and more specifically, to a method for manufacturing a high-voltage semiconductor device. Background technique [0002] In the current integrated circuit production process, there are many ways to produce high-voltage devices, one of which is to use a thicker gate dielectric layer to achieve high voltage, and the gate dielectric layer is mostly a gate oxide layer. Generally, before forming the gate oxide layer, an STI shallow trench isolation region must be formed in the active region. Due to the particularity of the structure of the STI shallow trench isolation region, the gate oxide layer formed on the corner of the STI shallow trench is usually smaller than the flat one. The active region is much thinner, which will lead to a lower breakdown voltage of the device, thereby reducing the reliability of the device, and from figure 1 It can be seen from the VGID (VG represents ...

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Problems solved by technology

[0011] Figure 5 For the electron micrograph of the gate oxide layer 106 on the corner of the STI shallow trench isolation region formed by the above method, it can be seen from the figure that the gate oxide layer (label 106a) on the corner of the STI shallow trench isolation region formed in the prior art The area shown) is still relatively thin, the breakdown voltage of the tested device is still low, and the device performance is still unstable

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