Mixed crystal face three-strain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device and manufacturing method thereof
A technology of mixed crystal planes and integrated devices, which is applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the limitations, the mobility cannot be optimized at the same time, and the mobility of Si material carrier material is low, etc. question
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Embodiment 1
[0116] Embodiment 1: Prepare 22nm mixed crystal surface three-strain BiCMOS integrated device and circuit, the specific steps are as follows:
[0117] Step 1, SOI substrate material preparation.
[0118] (1a) Select the N-type doping concentration as 1×10 15 cm -3 The Si wafer with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;
[0119] (1b) Select the P-type doping concentration as 1×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the lower layer;
[0120] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;
[0121] (1d) SiO on the surface of the lower and upper substrate materials after...
Embodiment 2
[0181] Embodiment 2: Prepare 30nm mixed crystal plane three-strain BiCMOS integrated device and circuit, the specific steps are as follows:
[0182] Step 1, SOI substrate material preparation.
[0183] (1a) Select the N-type doping concentration as 3×10 15 cm -3 The Si wafer with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;
[0184] (1b) Select the P-type doping concentration as 3×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the lower layer;
[0185] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the substrate material of the lower layer and the upper layer of the active layer after injecting hydrogen, respectively;
[0186] (1d) SiO on the surface of the l...
Embodiment 3
[0246] Embodiment 3: Preparation of 45nm mixed crystal plane three-strain BiCMOS integrated device and circuit, the specific steps are as follows:
[0247] Step 1, SOI substrate material preparation.
[0248] (1a) Select the N-type doping concentration as 5×10 15 cm -3 The Si sheet with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;
[0249] (1b) Select the P-type doping concentration as 5×10 15 cm -3 The Si wafer with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the lower layer;
[0250] (1c) Using a chemical mechanical polishing (CMP) process to polish the lower layer and the surface of the upper substrate material after hydrogen injection;
[0251] (1d) SiO on the surface of the lower and upper substrate materials after polis...
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