Mixed crystal face three-strain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device and manufacturing method thereof

A technology of mixed crystal planes and integrated devices, which is applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the limitations, the mobility cannot be optimized at the same time, and the mobility of Si material carrier material is low, etc. question

Inactive Publication Date: 2012-10-17
XIDIAN UNIV
View PDF2 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At the same time, NMOS devices and PMOS devices are prepared on the same crystal plane, and their mobility cannot be optimized at the same time.
[0007] Due to the low mobility of Si materials, the performance of integrated circuits manufactured using Si BiCMOS technology, especially the frequency performance, is greatly limited; for SiGe BiCMOS technology, although the bipolar transistor uses SiGe HBT devices , but Si CMOS is still used for unipolar devices that restrict the improvement of the frequency characteristics of BiCMOS integrated circuits, so these limit the further improvement of the performance of BiCMOS integrated circuits

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Mixed crystal face three-strain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0116] Embodiment 1: Prepare 22nm mixed crystal surface three-strain BiCMOS integrated device and circuit, the specific steps are as follows:

[0117] Step 1, SOI substrate material preparation.

[0118] (1a) Select the N-type doping concentration as 1×10 15 cm -3 The Si wafer with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0119] (1b) Select the P-type doping concentration as 1×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the lower layer;

[0120] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;

[0121] (1d) SiO on the surface of the lower and upper substrate materials after...

Embodiment 2

[0181] Embodiment 2: Prepare 30nm mixed crystal plane three-strain BiCMOS integrated device and circuit, the specific steps are as follows:

[0182] Step 1, SOI substrate material preparation.

[0183] (1a) Select the N-type doping concentration as 3×10 15 cm -3 The Si wafer with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0184] (1b) Select the P-type doping concentration as 3×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the lower layer;

[0185] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the substrate material of the lower layer and the upper layer of the active layer after injecting hydrogen, respectively;

[0186] (1d) SiO on the surface of the l...

Embodiment 3

[0246] Embodiment 3: Preparation of 45nm mixed crystal plane three-strain BiCMOS integrated device and circuit, the specific steps are as follows:

[0247] Step 1, SOI substrate material preparation.

[0248] (1a) Select the N-type doping concentration as 5×10 15 cm -3 The Si sheet with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0249] (1b) Select the P-type doping concentration as 5×10 15 cm -3 The Si wafer with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the lower layer;

[0250] (1c) Using a chemical mechanical polishing (CMP) process to polish the lower layer and the surface of the upper substrate material after hydrogen injection;

[0251] (1d) SiO on the surface of the lower and upper substrate materials after polis...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
Login to view more

Abstract

The invention discloses a mixed crystal face three-strain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device and a manufacturing method of the mixed crystal face three-strain BiCMOS integrated device. The method comprises the following steps of: manufacturing an SIO (Silicon On Insulator) substrate, etching a bipolar device active region on the substrate, continuously growing N-Si, P-SiGe, N-Si layers in the area, manufacturing deep trench isolation, manufacturing a collector region, a base region and an emitter region, forming a collector, base and emitter contact region, and forming a SiGe HBT (Heterojunction Bipolar Transistor) device; etching a deep trench in the area of an NMOS (N-Channel Metal Oxide Semiconductor) device, wherein a selective growth crystal face is (100) strain Si epitaxial layer, and manufacturing a strain Si channel NMOS device in the region; and in an active region of a PMOS (P-Channel Metal Oxide Semiconductor) device, the selective growth crystal face is (110) strain SiGe epitaxial layer, and preparing the PMOS device in the region. The BiCMOS device has a full face structure, and the characteristics that the electronic mobility of a tensile strain Si material is higher than that of a body Si material and the hole mobility of the compressive strain SiGe material is higher than that of the body Si material and the influence of the crystal face on the mobility are fully utilized; and moreover, the performance-enhanced mixed crystal face three-strain BiCMOS integrated device and a circuit of the performance-enhanced mixed crystal face three-strain BiCMOS integrated device are manufactured.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a mixed crystal plane three-strain BiCMOS integrated device and a preparation method. Background technique [0002] In the contemporary era of highly developed information technology, microelectronic technology represented by integrated circuits is the key to information technology. As the fastest-growing, most influential and most widely used technology in human history, integrated circuits have become an important symbol to measure a country's scientific and technological level, comprehensive national strength and national defense strength. [0003] "Moore's Law", which has had a huge impact on the development of the microelectronics industry, states that the number of transistors on an integrated circuit chip doubles approximately every 18 months, and the performance also doubles. For more than 40 years, the world's microelectronics indus...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/06H01L21/8249
Inventor 张鹤鸣宋建军王海栋周春宇胡辉勇宣荣喜舒斌郝跃
Owner XIDIAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products