TSV structure applicable to adapter board and preparation method of TSV structure

Abstract

The invention relates to a TSV structure applicable to an adapter board and a preparation method of the TSV structure. The TSV structure comprises a substrate and is characterized in that TSV deep holes are formed in the substrate, the side wall and the bottom wall of each TSV deep hole are provided with first insulating layers, second insulating layers are arranged on the surfaces of the first insulating layers, diffusion blocking layers are arranged on the surfaces of the second insulating layers, seed layers are arranged on the surfaces of the diffusion blocking layers, and the TSV deep holes are filled with conductive metal. The preparation method of the TSV structure applicable to the adapter board comprises the following steps that (1) the substrate is etched to form the TSV deep holes; (2) silicon dioxide is grown on the front surface of the substrate in a thermal oxidation mode so that the first insulating layers can be obtained, TEOS is deposited on the surfaces of the first insulating layers by adopting PECVD or SACVD or APCVD so that the second insulating layers can be obtained, then, the diffusion blocking layers are deposited on the surfaces of the second insulating layers, the seed layers are deposited on the surfaces of the diffusion blocking layers, and finally, the TSV deep holes are filled with the conductive metal. The TSV structure applicable to the adapter board is simple in process, low in cost and good in quality, and improves uniformity and insulativity of the insulating layers of silicon via holes.

Description

technical field [0001] The invention relates to a TSV structure suitable for an adapter board and a preparation method thereof, in particular to a microelectronic packaging technology / through-silicon via (TSV) structure of a semiconductor or solid device. Background technique [0002] TSV stands for Through Si via in the field of semiconductor microelectronics. In the process of 3D IC packaging and MEMS packaging, due to the use of multi-layer chip interconnection, it is necessary to punch holes through the entire chip to achieve electrical connection. [0003] The development of integrated circuits in terms of integration has always followed "Moore's Law", and as integrated circuit technology entered the era of 32nm technology, the complexity of the system and the investment cost of equipment have risen sharply, and the continuity of "Moore's Law" has been seriously affected. restrict. Meanwhile, conventional 2D miniaturization strategies have reached the limits of perfor...

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Problems solved by technology

When TSV uses a single insulating layer, in the subsequent outcropping process, due to the requirements of etching depth and etching rate, the etching solution often needs to use hydrofluoric acid + nitric acid + acetic acid / deionized water (HNA) system, However, this solution system will also etch the silicon dioxide (TEOS) insulating layer, and the etching options for silicon and TEOS are relatively small. Once the TEOS insulating layer is etched, the diffusion barrier layer Ti or TiN will be exposed to the etching process. In the solution, the etchant has a higher etching rate for Ti or TiN, and the results include: 1) Etching the filling metal (after the diffusion barrier layer such as Ti or TiN is etched, the etchant will immediately contact with 2) Severe undercutting of the diffusion barrier layer; 3) The complexity of the process and the increase in cost (because the above results will consider the use of other etching solutions or dry etching, other wet etching The etch rate of the liquid is slow, and the etching cost of the dry etching is higher for a larger depth)

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