A method for manufacturing a silicon epitaxial wafer of a high-power pin device

A technology of silicon epitaxial wafers and manufacturing methods, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of reducing the effective thickness of the epitaxial layer, low edge resistivity, uneven breakdown voltage and series resistance, etc. , to achieve the effect of reducing gas phase self-doping, ensuring performance and yield, and reducing the transition zone width

Active Publication Date: 2018-02-02
NANJING GUOSHENG ELECTRONICS
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Problems solved by technology

However, in the actual growth process, due to the solid-state diffusion of impurity atoms from the high-concentration substrate to the epitaxial layer and HCl corrosion before epitaxy, H 2 The high temperature during processing and epitaxial growth causes the impurity atoms of the heavily doped substrate to evaporate from the solid phase to the gas phase of the reaction chamber from the front, edge and back. Although blown off by a large flow of gas, some impurities still remain on the substrate. In the stagnant layer on the surface, it enters the epitaxial layer during epitaxial growth to form gas-phase self-doping, which causes the impurity concentration at the interface between the substrate and the epitaxial layer to be too high, causing the transition zone to widen, thereby reducing the effective thickness of the epitaxial layer
At the same time, gas-phase self-doping has a great influence on the uniformity of radial resistivity distribution on the surface of the epitaxial layer, so that the center resistivity of the epitaxial wafer is high and the edge resistivity is low. When the device is made, its breakdown voltage Vbc is large in the middle and small at the edge. , resulting in uneven breakdown voltage and series resistance

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Embodiment Construction

[0012] The present invention is described in detail below by specific embodiment:

[0013] The method for manufacturing silicon epitaxial wafers for PIN tubes in this embodiment uses N-type polished wafers heavily doped with As, with resistivity ≤ 0.003 Ω·cm, local flatness ≤ 1.5 mm, and no back-sealing oxide layer on the back. The process is as follows: 1. Use the principle of mass transfer to transfer polysilicon from the graphite base to the back of the substrate to achieve the purpose of back encapsulation; 2. Select the appropriate gas corrosion flow rate and gas corrosion time to reduce the gas corrosion impurities in the epitaxial reaction chamber 3. After gas corrosion, choose hydrogen with variable temperature and flow rate to purge the epitaxial reaction chamber to reduce the impurity concentration in it; 4. The first layer of epitaxial growth: at high The surface of the substrate with a lower temperature is used to grow an intrinsic epitaxial layer for encapsulatio...

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Abstract

The invention provides a manufacturing method of a silicon epitaxial wafer of a large-power PIN device. The method is that a highly As-doped N type <100> polished wafer of which the resistivity does not exceeds 0.003 ohm / cm and local flatness does not exceeds 1.5mm and the rear surface is free of a back seal oxide layer is adopted. The manufacturing method of the silicon epitaxial wafer of the large-power PIN device has the advantages that 1, polycrystalline silicon is transferred from a graphite base to the rear surface of a substrate by the mass transfer principle, so as to reach the back enveloping purpose; 2, proper atmospheric corrosion flow and atmospheric corrosion time are selected and the gas phase concentration of atmospheric corrosion impurities in an epitaxial reaction chamber is reduced so as to reduce self doping under epitaxial growth; 3, after atmospheric corrosion, variable temperature and flow hydrogen is selected to purge the epitaxial reaction chamber; 4, during the growth of a first epitaxial layer, an intrinsic epitaxial layer grows under relatively low temperature to envelope the high-concentration substrate surface, and the growth temperature, rate and time are controlled to reach an ideal enveloping layer; and 5, during the growth of a second epitaxial layer, an epitaxial layer of which the surface concentration is below 10E13cm-3 grows under a low temperature.

Description

technical field [0001] The invention relates to a silicon epitaxial wafer in the field of semiconductor silicon materials, in particular to a method for manufacturing a silicon epitaxial wafer of a high-power PIN device. Background technique [0002] PIN diode (positive-intrinsic-negative diode, abbreviated as PIN diode) is a kind of light that absorbs light radiation and generates photocurrent in the PN junction between two semiconductors, or in the vicinity of the junction between semiconductor and metal. Detector. Ordinary diodes are composed of PN junctions, and a thin layer of low-doped intrinsic (Intrinsic) semiconductor layer is added between P and N semiconductor materials. The diode of this P-I-N structure is a PIN device. PIN device is a common semiconductor device widely used in the fields of microwave, electric power and optoelectronics. It is mostly used as microwave switch, microwave attenuator, microwave limiter, digital phase shifter, etc. High-power rectif...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/329
CPCH01L21/02381H01L21/02532H01L29/6609
Inventor 金龙李国鹏谭卫东
Owner NANJING GUOSHENG ELECTRONICS
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