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A kind of semiconductor device and its manufacturing method and electronic device

A semiconductor and device technology, applied in the field of semiconductor devices and their manufacturing methods and electronic devices, can solve problems such as plasma damage of NMOS devices, achieve the effects of avoiding plasma damage, improving performance and yield

Active Publication Date: 2018-07-20
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

According to the manufacturing method, the step of removing the sacrificial layer in the NMOS region by dry etching will cause plasma damage to the NMOS device

Method used

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  • A kind of semiconductor device and its manufacturing method and electronic device
  • A kind of semiconductor device and its manufacturing method and electronic device
  • A kind of semiconductor device and its manufacturing method and electronic device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0035] The following will combine Figure 2A-2I The method for preparing the semiconductor device of the present invention is described in detail. Such as Figure 2AAs shown, a semiconductor substrate 200 is provided, and the semiconductor substrate 200 may include any semiconductor material, which may include but not limited to: Si, SiC, SiGe, SiGeC, Ge alloy, GeAs, InAs, InP, and other III-V Or II-VI compound semiconductors. Also optionally, the semiconductor substrate 200 may include an epitaxial layer. The semiconductor substrate 200 may also include an organic semiconductor or a layered semiconductor such as Si / SiGe, silicon-on-insulator (SOI), or SiGe-on-insulator (SGOI).

[0036] The semiconductor substrate 200 includes various isolation structures 201 that may include different structures and be formed by different processing techniques. For example, the isolation features may include shallow trench isolation features (STI). The semiconductor substrate 200 also in...

Embodiment 2

[0070] Next, the manufacturing of the entire semiconductor device can be completed through subsequent processes, including: forming another interlayer dielectric layer on the interlayer dielectric layer 202 to cover the tops of the metal gates 215A, 215B; Contact holes are formed in the interlayer dielectric layer to expose the tops of the metal gates 215A, 215B and the tops of the source / drain regions; a salicide is formed at the bottom of the contact holes and filled with metal (usually tungsten ) forming a contact plug connecting the subsequently formed interconnection metal layer and the self-aligned silicide in the contact hole; forming a plurality of interconnection metal layers, usually using a double damascene process; forming a metal pad for subsequent Wire bonding when implementing device packaging.

Embodiment 3

[0072] An embodiment of the present invention provides an electronic device, which includes an electronic component and a semiconductor device electrically connected to the electronic component. Wherein, the semiconductor device is a semiconductor device manufactured according to the method for manufacturing a semiconductor device described in Embodiment 1, or is the semiconductor device described in Embodiment 2.

[0073] The electronic device of this embodiment can be any electronic product or equipment such as mobile phone, tablet computer, notebook computer, netbook, game console, TV set, VCD, DVD, navigator, camera, video recorder, voice recorder, MP3, MP4, PSP, etc. , can also be any intermediate product including the semiconductor device. Wherein, the electronic component may be any component, which is not limited here.

[0074] The electronic device according to the embodiment of the present invention has lower power consumption due to the use of the above-mentioned s...

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Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and an electronic apparatus. The method comprises the steps as follows: providing a semiconductor substrate with a first region and a second region, wherein both the first region and the second region include a virtual gate; removing the virtual gates to form a first trench and a second trench; sequentially depositing a high-K dielectric layer, a cover layer, a barrier layer, a P-type work function metal layer and a sacrifice layer on the semiconductor substrate; removing the sacrifice layer in the second region; forming a spacer protection layer on the semiconductor substrate; removing the spacer protection layer in the second region; removing the sacrifice layer in the second trench of the second region; removing the P-type work function metal layer in the second region; removing the sacrifice layer and the spacer protection layer in the first region; and sequentially depositing an N-type work function metal layer and a metal electrode layer on the semiconductor substrate. According to the manufacturing method of the invention, plasma damage to an NMOS device is avoided, and further, the performance and yield of the semiconductor device are improved.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background technique [0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. At present, since the semiconductor industry has advanced to the nanotechnology process node in the pursuit of high device density, high performance and low cost, especially when the size of semiconductor devices is reduced to 20nm or below, the fabrication of semiconductor devices is limited by various physical limits. [0003] The main device in integrated circuits (ICs), especially VLSIs, is metal-oxide-semiconductor field-effect transistors (MOSs). High performance and more functional integrated circuits require greater component density, and t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238H01L27/092
Inventor 赵杰
Owner SEMICON MFG INT (SHANGHAI) CORP