Semiconductor structure and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems such as the need to improve the electrical performance of SRAM devices, and achieve the effects of avoiding adverse effects, optimizing electrical performance, and reducing the degree of diffusion.

Active Publication Date: 2017-12-19
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, the electrical performance of SRAM devi

Method used

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  • Semiconductor structure and manufacturing method thereof
  • Semiconductor structure and manufacturing method thereof
  • Semiconductor structure and manufacturing method thereof

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Embodiment Construction

[0036] It can be seen from the background art that the electrical performance of the SRAM device formed in the prior art needs to be improved. Combined with the manufacturing method of SRAM devices, the reasons are analyzed:

[0037] refer to Figure 1 to Figure 4 , shows a schematic structural diagram corresponding to each step in a manufacturing method of a semiconductor structure.

[0038] refer to figure 1, providing a base (not marked), the base includes a substrate 100 and a fin (not marked) protruding from the substrate 100 , the substrate 100 includes an NMOS region I and a PMOS region II. The NMOS region I is used to form a pull-down (PD, Pull Down) transistor, and the PMOS region II is used to form a pull-up (PU, Pull Up) transistor.

[0039] Specifically, the fin located in the NMOS region I is the first fin 110 , and the fin located in the PMOS region II is the second fin 120 .

[0040] refer to figure 2 , forming a P-type work function film 130 covering the ...

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Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof. The method comprises steps: a base is provided, wherein the base comprises a substrate and a fin part protruding against the substrate, the substrate comprises a first area and a second area, and the first area and the second area are used for forming different types of transistors; a gate dielectric layer covering the top part and the side wall of the fin part is formed; a blocking layer is formed on the gate dielectric layer at the junction of the first area and the second area, wherein the blocking layer at least covers the gate dielectric layer in the second area at the junction; a second work function layer is formed on the gate dielectric layer in the second area and the blocking layer; and a first work function layer is formed on the gate dielectric layer in the first area. The blocking layer is firstly formed on the gate dielectric layer at the junction of the first area and the second area, the blocking layer at least covers the gate dielectric layer in the second area at the junction, the blocking layer can reduce the diffusion degree of metal ions of the first work function layer in the second work function layer, and bad influences on the performance of the second work function layer can also be avoided.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof. Background technique [0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three types: logic, memory and analog circuits, among which memory devices account for a considerable proportion of integrated circuit products. With the development of storage technology, various types of semiconductor memories have appeared, such as Static Random Access Memory (SRAM, Static Random Access Memory), Dynamic Random Access Memory (DRAM, Dynamic Random Access Memory), Erasable Programmable Read-Only Memory (EPROM) EPROM, Erasable Programmable Read-Only Memory), Electrically Erasable Programmable Read-Only Memory (EEPROM, Electrically Erasable Programmable Read-Only) and flash memory (Flash). Since the SRAM has the advantages of low power consumption and fast working speed, more and more...

Claims

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Application Information

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IPC IPC(8): H01L27/11H01L27/092H01L21/8238H01L21/8244
CPCH01L27/0924H01L21/823821H01L21/823842H10B10/12
Inventor 周飞
Owner SEMICON MFG INT (SHANGHAI) CORP
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