Distributed peripheral bus system of strict access and sampling time and control method thereof

A technology of sampling time and peripheral bus, applied in the direction of program control, comprehensive factory control, comprehensive factory control, etc., can solve problems such as low speed, inability to achieve accuracy of fieldbus, complex bus scheduling, etc., and achieve the effect of increasing data transmission speed

Active Publication Date: 2019-07-05
朱磊
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The current mainstream fieldbus speed, especially the board-level fieldbus speed is very low, Profibus-DP represents one of the highest speeds in this field, but its speed is not higher than 12Mbps
[0006] 2) The certainty of transmission time needs to be improved
Complicated and high-speed industrial production control, electric high-voltage relay protection and other fast automatic devices require IO data to be sampled synchronously with an error of less than 1 μ second under the requirements of considerable capacity. However, the current fieldbus cannot achieve this accuracy and is limited to these field application
At the same time, there are many types of data involved, such as real-time IO data, emergency control data, historical curve data, historical event data, wave recording data, IO management data, diagnostic data, etc., and the transmission time determinism and priority control are different. , the current fieldbus technology still has a lot of deficiencies
[0007] 3) The data transfer mechanism needs to be simplified
The current fieldbus also has deficiencies in the classification of transmission data, the arbitration of the right to use the serial bus, and the data interaction mechanism; the FF bus uses the transmission token to arbitrate the right to use the bus, and the PROFIBUS uses the token time slice rotation of the master station. Priority data considers multi-segment transmission, as well as the master-slave polling mechanism, as well as the CAN bus multi-control field field and short data frame mode, etc., resulting in complex bus scheduling and reduced effective utilization of bus bandwidth

Method used

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  • Distributed peripheral bus system of strict access and sampling time and control method thereof
  • Distributed peripheral bus system of strict access and sampling time and control method thereof
  • Distributed peripheral bus system of strict access and sampling time and control method thereof

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Embodiment Construction

[0050] The present invention will be further described in detail below in conjunction with the accompanying drawings and the embodiments of the present invention.

[0051] figure 1 It is a schematic diagram of a distributed peripheral bus system with strict access and sampling time according to an embodiment of the present invention.

[0052] Such as figure 1 As shown, the distributed peripheral bus system with strict access and sampling time, namely

[0053] FASTDP-BUS bus system, which includes a single bus master and one or more bus slaves. The physical layer of the bus system adopts dual redundant low-voltage differential signal (LVDS) bus technology, and the data transmission rate can reach 100Mbps; the data link layer adopts the field programmable gate array (FPGA) implementing the FASTDP-BUS link protocol Or the FASTDP-BUS protocol control chip is implemented, and the protocol control chip is implemented by an application-specific integrated circuit (ASIC); its appli...

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Abstract

The invention discloses a distributed peripheral bus system of strict access and sampling time and a control method thereof. The system comprises one unibus main station and at least one bus slave station. The physical layer of the system adopts a dual-redundant low voltage differential signal (LVDS) bus technology; A data link layer is implemented through using a field programmable gate array (FPGA) capable of realizing a FASTDP-BUS link protocol or a FASTDP-BUS protocol control chip. The FASTDP-BUS protocol control chip is implemented through an application-specific integrated circuit (ASIC)mode. An application layer uses a FASTDP-BUS application layer protocol specification and is realized through mapping a FPGA or FASTDP-BUS control chip to a CPU of an internal address space via an industry standard architecture (ISA) bus. In the invention, data access time determinacy based on a bus and the time determinacy of analog sampling can be effectively increased, and simultaneously a thebus data mechanism is simplified.

Description

technical field [0001] The invention relates to field bus intelligent control technology, in particular to a distributed peripheral bus system with strict access and sampling time and a control method thereof. Background technique [0002] The field bus interconnects the sensors, measurement and control units and automation control systems distributed in the field, realizes the intercommunication of input and output (IO) data, and provides strong support for the information transmission and information control of the industrial automation control system. There are hundreds of types of fieldbus, many of which have become international standards, such as: PROFIBUS, Controller Area Network (CAN, Controller Area Network), Device Net, INTERBUS, Foundation Fieldbus (FF, FoudationField Bus), etc. play an important role in the system. [0003] The PROFIBUS bus adopts the token time slice rotation of the master station. Its high-priority data considers multi-segment transmission and...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05B19/418
CPCG05B19/4186Y02P90/02
Inventor 朱磊
Owner 朱磊
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