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Oxidation level heterogeneous p-n junction structure device and preparation method thereof

A heterogeneous and horizontal technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as complex process, high cost, and increased lattice defects, and achieve high carrier concentration and low production cost , The effect of high production efficiency

Active Publication Date: 2020-07-14
SOUTH UNIVERSITY OF SCIENCE AND TECHNOLOGY OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, there are many defects in the growth method, such as complex process, uneven p-n junction, and difficulty in doping control. Then form a p-n junction by recrystallization
The same alloy method also has disadvantages, such as the p-n junction is not smooth, the junction depth and the size of the junction are not easy to control, etc.; the ion implantation method refers to converting impurity atoms into ionized impurity ions first, and then injecting them in an extremely strong electric field Shoot the semiconductor at a high speed so that it can enter the interior of the semiconductor to achieve the purpose of doping
Although the ion implantation method overcomes the shortcomings of the first two methods, it has extremely high requirements for equipment, high cost, and low production efficiency; the diffusion method is currently the most commonly used method for manufacturing p-n junctions, which refers to the use of impurities at high temperature. Diffuse downward into the semiconductor, so that p-type impurities enter the n-type semiconductor or n-type impurities enter the p-type semiconductor to form a p-n junction
This method can not only precisely control the junction depth and junction area, but also maintain the flatness of the junction surface and doping concentration, but the high temperature introduced by the diffusion method when preparing the p-n junction may increase the lattice defects of the material

Method used

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  • Oxidation level heterogeneous p-n junction structure device and preparation method thereof
  • Oxidation level heterogeneous p-n junction structure device and preparation method thereof
  • Oxidation level heterogeneous p-n junction structure device and preparation method thereof

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Effect test

Embodiment 1

[0047] This embodiment provides a horizontal heterogeneous p-n junction structure, and the p-n junction structure device includes: a sapphire substrate, an n-type gallium nitride layer, a p-type gallium oxide layer embedded in the n-type gallium nitride layer, and a metal electrode . Such asfigure 1 Shown is a schematic diagram of an oxidation level heterogeneous p-n junction structure device. The bottom layer is a sapphire substrate 1, and the substrate 1 can also be a silicon substrate, a silicon carbide substrate, a diamond substrate, an aluminum nitride substrate, a gallium nitride homogeneous substrate, or boron nitride, graphene, Flexible substrates such as copper nickel. On the substrate 1 are alternately arranged n-type gallium nitride layers 2 and p-type gallium oxide layers 4 . The carrier concentration of the p-type gallium oxide layer 4 is 1×10 11 ~1×10 19 / cm 3 . The n-type gallium nitride layer can also be other n-type III-V compounds such as n-type indium ...

Embodiment 2

[0049] This embodiment provides the preparation method of the oxidation level heterogeneous p-n junction structure device of embodiment 1. It mainly includes the following steps:

[0050] Step (1), growing a layer of n-type gallium nitride layer 2 on the sapphire substrate 1 with a thickness of 4 μm, figure 2 is a schematic diagram of the grown GaN layer, image 3 is the Hall test result of the grown gallium nitride layer, and the test result shows that the grown gallium nitride layer is an n-type gallium nitride layer.

[0051] Step (2), on the n-type gallium nitride layer, deposit a layer of aluminum oxide on the n-type gallium nitride layer as a mask 3 by atomic vapor deposition, Figure 4 It is a schematic diagram after depositing a mask layer on the n-type gallium nitride layer.

[0052] In step (3), by chemical vapor deposition, in the area not covered with the mask 3 on the n-type gallium nitride layer, the carrier concentration of thermal oxidation diffusion growth...

Embodiment 3

[0058] This embodiment provides a heterojunction field effect transistor device based on a horizontal heterogeneous p-n junction and a manufacturing method thereof. The heterojunction field effect transistor device comprises: a sapphire substrate 1 , an n-type gallium nitride layer 2 , a p-type gallium oxide layer 4 embedded in the n-type gallium nitride layer, and metal electrodes 5 , 6 , 7 . Such as Figure 12 Shown is a schematic diagram of a heterojunction field effect transistor device.

[0059] The preparation method of the heterojunction field effect transistor device specifically includes:

[0060] Step (1), growing a gallium nitride layer 2 on the sapphire substrate 1 with a thickness of 4 μm, figure 2 Schematic diagram of the grown GaN layer, image 3 It is the Hall test result of the grown gallium nitride layer, and the result shows that the grown gallium nitride layer is n-type.

[0061] Step (2), on the n-type gallium nitride layer 2, deposit a layer of alumi...

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Abstract

The invention discloses an oxidation level heterogeneous p-n junction structure device and a preparation method thereof, and belongs to the field of semiconductor devices. The oxidation level heterogeneous p-n junction structure device comprises a substrate, an n-type material layer, a p-type material layer embedded in the n-type material layer, and metal electrodes on the upper surfaces of the n-type material layer and the p-type material layer, wherein the selective growth of the p-type material layer is realized by covering the n-type material layer with the mask layer, a heterogeneous p-njunction structure in the horizontal direction can be obtained after the growth is finished, and the carrier concentration of the p-type material layer is 1*10<11> - 1*10<19> / cm<3>. The method is simple in process and wide in application range, and application of III-V group semiconductor materials such as gallium nitride and indium nitride is expected to be expanded.

Description

technical field [0001] The invention belongs to the field of semiconductors, in particular to a horizontal heterogeneous p-n junction structure and a preparation method thereof. Background technique [0002] With the rapid development of the semiconductor industry, the oxide semiconductor p-n junction has become a research hotspot. Due to the intrinsic defects of oxides and the limitation of preparation technology, stable and high-performance p-type hole-conducting materials are scarce. For most oxide crystals, the n-type semiconductor is easy to form, and the control of the carrier concentration in a large range has been realized through the doping of atoms such as Si and Sn. [0003] In recent studies, p-type oxide materials have become a research hotspot, and the preparation of many high-quality p-type materials has been preliminarily realized. As one of the important applications of p-type materials, the p-n junction occupies a very important position in the field of e...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L29/78H01L21/336H01L21/02H01L21/67
CPCH01L29/78H01L29/0684H01L29/66446H01L21/02565H01L21/02636H01L21/67248H01L21/67253
Inventor 方志来闫春辉蒋卓汛吴征远田朋飞张国旗
Owner SOUTH UNIVERSITY OF SCIENCE AND TECHNOLOGY OF CHINA
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