Semiconductor device and forming method thereof

Abstract

The invention discloses a semiconductor device and a forming method thereof. The semiconductor device comprises a substrate, a fin part arranged on the substrate, an isolation structure arranged on the substrate and covering part of the side wall of the fin part, and having the top surface lower than the top surface of the fin part, a gate structure arranged on the substrate and stretching across the fin part, conductive layers located on the two sides of the gate structure, an initial first hard mask layer located on a top surface of an end portion of the gate structure, second hard mask layers arranged on the top surfaces of the conductive layers on two sides of the center of the gate structure, a dielectric layer initially arranged on the initial first hard mask layer and the second hard mask layers, a first through hole formed in the dielectric layer, and having the bottom exposing the central top surface of the gate structure, a second through hole formed in the dielectric layer, and having the bottom exposing the top surfaces of the conductive layers on one side of the end of the gate structure, a first contact layer located in the first through hole, and a second contact layer =located in the second through hole; the semiconductor device provided by the invention has good performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof. Background technique [0002] The scaling of feature sizes in integrated circuits has been the driving force behind the growing semiconductor industry over the past few decades. Scaling to smaller and smaller feature sizes enables an increased density of functional units on the limited real estate of a semiconductor chip. For example, reducing transistor size allows for an increased number of memory or logic devices to be included on a chip, resulting in the manufacture of products with increased capacity. But the drive to greater capacity is not without its problems. The need to optimize the performance of each device is becoming increasingly apparent. [0003] In the manufacture of integrated circuit devices, such as multi-gate transistors, are becoming more common as device dimensions continue to shrin...

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Problems solved by technology

[0004] But shrinking the size of multi-gate transistors is not without its consequences. As the size of these basic building blocks of microelectronic circuits decreases, and as the absolute number of basic building blocks fabricated in a given area increases, the number of building blocks used to form them increases. The constraints of the patterning lithography process become difficult to overcome

The electrical performance of multi-gate transistors in the prior art still needs to be improved

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