Gallium oxide field effect transistor power device with novel structure
A technology of gallium oxide field and gallium oxide, which is applied in the field of lateral devices and vertical devices, can solve the problems of restricting the development of gallium oxide power devices, unable to realize the superjunction structure of performance, and unsatisfactory voltage resistance effect, so as to improve performance and reduce Compared with on-resistance and power consumption, the effect of solving poor heat dissipation
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Embodiment 1
[0042] This embodiment provides a lateral gallium oxide field effect power transistor device, which has the characteristics of high withstand voltage and low specific on-resistance; its structure is as follows figure 1 shown, including:
[0043] N-type gallium oxide channel region 1-1, unintentionally doped or undoped buffer layer 1-8 under the n-type gallium oxide channel region, semi-insulating under unintentional doped or undoped buffer layer Or high purity gallium oxide substrate 1-9;
[0044] Two heavily doped N-type gallium oxide regions 1-2 located in the N-type gallium oxide channel region, the two heavily doped N-type gallium oxide regions are respectively connected with the metallized source (S) 1-6, the metallized drain Poles (D) 1-7 form ohmic contacts;
[0045] The trench gates (G) 1-4 located in the N-type gallium oxide channel region, the trench gates (G) are composed of an oxide layer (Al 2 O 3 ) and the polysilicon gate filled in the groove;
[0046] The ...
Embodiment 2
[0050] This embodiment provides a lateral gallium oxide field effect power transistor device, which has the characteristics of high withstand voltage, low specific on-resistance and good heat dissipation performance; its structure is as follows figure 2 shown, including:
[0051] N-type gallium oxide channel region 2-1, unintentionally doped or undoped buffer layer 2-8 under the n-type gallium oxide channel region, semi-insulating under unintentional doped or undoped buffer layer or high purity gallium oxide substrate 2-9;
[0052] Two heavily doped N-type gallium oxide regions 2-2 located in the N-type gallium oxide channel region, the two heavily doped N-type gallium oxide regions are respectively connected with the metallized source (S) 2-6 and the metallized drain The poles (D) 2-7 form an ohmic contact;
[0053] The oxide layer 2-3 above the N-type gallium oxide channel region, the plane gate (G) 2-4 above the oxide layer, the P-type doped diamond (or aluminum nitride,...
Embodiment 3
[0057] This embodiment provides a lateral gallium oxide field effect power transistor device, which has the characteristics of high withstand voltage, low specific on-resistance and good heat dissipation performance; its structure is as follows image 3 shown, including:
[0058] N-type gallium oxide channel region 3-1, unintentionally doped or undoped buffer layer 3-8 under the n-type gallium oxide channel region, semi-insulating under unintentional doped or undoped buffer layer or high purity gallium oxide substrate 3-9;
[0059] Two heavily doped N-type gallium oxide regions 3-2 located in the N-type gallium oxide channel region, the two heavily doped N-type gallium oxide regions are respectively connected with the metallized source (S) 3-6, the metallized drain Poles (D) 3-7 form ohmic contacts;
[0060] A trench gate (G) 3-4 located in the N-type gallium oxide channel region, the trench gate (G) consists of an oxide layer (Al 2 O 3 ) and the polysilicon gate filled in...
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