This application relates to a method for generating cross-architecture computationally intensive fusion operators based on
hardware abstraction. It constrains and determines the operator subgraph according to preset legality rules, establishes a unified semantic abstraction, defines the fusion operator as a coordinate-driven pure function, and encapsulates auxiliary
tensor memory access handles and
layout geometry information through runtime context. A backend normalization layer is used to semantically reinterpret the accumulator
layout and thread organization of different hardware vendors during
compile time, and cross-platform vectorization primitives are invoked to
mask the differences in backend
instruction set architectures. Arithmetic logic is downgraded to a sequence of instructions executed within a scalar scope. The abstract vector view is first decomposed into independent scalar elements, arithmetic instructions are generated in the scalar dimension, the calculation results are then reorganized into a vector register, and finally, an address expression is constructed by deriving the effective step size to
handle broadcast and indexing logic, generating fusion code that can access the underlying vendor's computationally intensive kernel, thus improving development efficiency.