Metal-semiconductor field-effect transistor with gate lower buffer layer structure and manufacturing method

A field effect transistor, metal semiconductor technology, applied in the field of electronics, can solve the problems of the characteristic frequency and the highest oscillation frequency of the device, reduce the reliability of the device, affect the gain of the device, etc., so as to overcome the negative effects, improve the breakdown voltage, and improve the output. effect of current

Inactive Publication Date: 2011-12-21
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the disadvantage of this patent application is that the gate field plate and the drain field plate will introduce additional gate-drain capacitance, which will reduce the characteristic frequency and the highest oscillation frequency of the device, and affect the gain of the device when it works in the high frequency band.
The shortcomings of this technology are: the structure proposes that the field plate electrode needs to bypass the gate electrode to realize the connection in the layout layout, which increases the complexity of the layout and reduces the yield of large gate width devices; on the other hand, the invention There are multiple metal electrodes and dielectric materials that are electrically connected, which reduces the reliability of the device
The disadvantage of this technology is that multiple thin line patterns are introduced into the channel layer, which destroys the original flat structure of the channel layer and makes the potential and electric field distribution in the channel layer complicated.
For field effect devices that have been mainstream in recent years, it is difficult to accurately etch complex and small patterns, and the contradiction between its structure and the current technology level restricts the practical application of this structure

Method used

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  • Metal-semiconductor field-effect transistor with gate lower buffer layer structure and manufacturing method
  • Metal-semiconductor field-effect transistor with gate lower buffer layer structure and manufacturing method
  • Metal-semiconductor field-effect transistor with gate lower buffer layer structure and manufacturing method

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0033] Embodiment 1, comprises the steps:

[0034] Step 1, substrate pretreatment.

[0035] Use acetone, methanol, and deionized water to clean the semi-insulating substrate sample in sequence, and then use the standard RCA cleaning process in the microelectronics process to remove impurities and oxide layers on the surface of the sample.

[0036] Step 2, growing the buffer layer.

[0037] On the front of the pretreated substrate sample, a homogeneous P-type buffer layer is grown by metal oxide semiconductor chemical vapor deposition. 15 cm -3 .

[0038] Step 3, growing a channel layer.

[0039] On the buffer layer, a homogeneous N-type channel layer is grown by metal oxide semiconductor chemical vapor deposition, with a thickness of 0.25 microns, phosphorus is used as impurity doping, and the doping concentration is 1.5×10 17 cm -3 .

[0040] Step 4, growing a buffer layer under the gate.

[0041] On the buffer layer, a homogeneous N-type buffer layer under the gate is ...

Embodiment 2

[0050] Embodiment 2, comprises the steps:

[0051] Step 1, substrate pretreatment.

[0052] Use acetone, methanol, and deionized water to clean the semi-insulating substrate sample in sequence, and then use the standard RCA cleaning process in the microelectronics process to remove impurities and oxide layers on the surface of the sample.

[0053] Step 2, growing the buffer layer.

[0054] On the front of the pretreated substrate sample, a homogeneous P-type buffer layer was grown by metal oxide semiconductor chemical vapor deposition. 15 cm -3 .

[0055] Step 3, growing a channel layer.

[0056] On the buffer layer, a homogeneous N-type channel layer is grown by metal oxide semiconductor chemical vapor deposition, with a thickness of 0.3 microns, phosphorus is used as doping impurity, and the doping concentration is 2.5×10 17 cm -3 .

[0057] Step 4, growing a buffer layer under the gate.

[0058] On the buffer layer, a homogeneous N-type buffer layer under the gate i...

Embodiment 3

[0067] Embodiment 3, comprises the steps:

[0068] Step 1, substrate pretreatment.

[0069] Use acetone, methanol, and deionized water to clean the semi-insulating substrate sample in sequence, and then use the standard RCA cleaning process in the microelectronics process to remove impurities and oxide layers on the surface of the sample.

[0070] Step 2, growing the buffer layer.

[0071] A homogeneous P-type buffer layer was grown on the front of the pretreated substrate sample by metal oxide semiconductor chemical vapor deposition. 15 cm -3 .

[0072] Step 3, growing a channel layer.

[0073] On the buffer layer, a homogeneous N-type channel layer is grown by metal oxide semiconductor chemical vapor deposition, with a thickness of 0.35 microns, phosphorus is used as impurity doping, and the doping concentration is 3.5×10 17 cm -3 .

[0074] Step 4, growing a buffer layer under the gate.

[0075] On the buffer layer, a homogeneous N-type buffer layer under the gate i...

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PUM

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Abstract

The invention relates to a metal-semiconductor field effect transistor with an under-grid buffer layer structure and a manufacturing method; the transistor comprises a semi-insulating substrate, a buffer layer, a channel layer, an under-grid buffer layer, a source electrode cap layer, a drain electrode cap layer, a source electrode, a drain electrode and a grid electrode, wherein the under-grid buffer layer, the source electrode cap layer and the drain electrode cap layer are sequentially formed on the channel layer; the under-grid buffer layer forms a raised platform on the channel layer; and the grid electrode is formed on the raised platform. The manufacturing method of the transistor comprises the following steps of: sequentially growing a P type buffer layer, an N type channel layer and an N type under-grid buffer layer on the semi-insulating substrate; carrying out high concentration N type ion implantation on regions of both ends of the under-grid buffer layer corresponding to the source electrode and the drain electrode to form a source electrode cap layer and a drain electrode cap layer; etching a part of the under-grid buffer layer which is positioned between a grid source and a grid drain; and manufacturing the source electrode and the drain electrode on the source electrode cap layer and the drain electrode cap layer, and manufacturing the grid electrode on the under-grid buffer layer. The transistor of the invention can increase the power density and frequency response of a microwave power amplifier circuit and a microwave power amplifier system; and the manufacturing process is simple.

Description

technical field [0001] The invention belongs to the field of electronic technology, and further relates to a metal-semiconductor field-effect transistor with a gate lower buffer layer structure and a manufacturing method in the field of microelectronic technology. The transistor provided by the invention can be applied to microwave power amplifier circuits and systems to improve the power density and frequency response of the circuits and systems. Background technique [0002] With the rapid development of wireless communication technology, the demand for high-power microwave applications is increasingly urgent. In recent years, metal-semiconductor field-effect transistors have been widely used in microwave-band communication and radar devices, and the performance of circuits and systems has been continuously improved. At present, achieving high power output at high operating frequencies such as S-band (3GHz) and X-band (8GHz) has become the mainstream direction of metal-se...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L29/772H01L21/335
Inventor 宋坤柴常春杨银堂张现军
Owner XIDIAN UNIV
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