TSV (through silicon via) three-dimensional integration interconnection structure based on SOI (silicon on insulator)

Abstract

The invention discloses a TSV three-dimensional integration interconnection structure based on an SOI. The interconnection structure comprises a barrier layer, a side wall insulation layer, and a conductive filler, wherein a copper pillar is the conductive filler; the barrier layer and the side wall insulation layer sequentially wrap the outer wall of the copper pillar; the copper pillar penetrates through a top silicon layer, a buried oxide layer and substrate silicon of the SOI longitudinally to form the TSV; the TSV above the buried oxide layer has a diameter W1; the TSV below the buried oxide layer has a diameter W2 smaller than W1, and is coaxial with the TSV above the buried oxide layer. The interconnection structure provided by the invention not only can realize three-dimensional integration of the SOI-based process device and meet the process requirement for TSV three-dimensional integration of a hardened device and a high-voltage / low-leakage device, but also can reduce the influences of Notching effect on the subsequent side wall insulation process, thereby improving breakdown voltage, enhancing reliability of an SOI-based TSV three-dimensional integration device, saving chip area, and lowering development cost.

Description

technical field [0001] The invention relates to the technical field of microelectronics. Background technique [0002] Usually, the TSV three-dimensional integrated interconnection structure is realized on a single crystal silicon wafer, and the "inverted ladder" structure formed by KOH anisotropic etching or the "I" structure based on ICP dry etching are mostly used (see figure 1 ). The main disadvantages of using the above interconnection structure are: [0003] (1) The above-mentioned interconnection structures are all implemented on single crystal silicon wafers, and the etching materials are all silicon, which cannot meet the etching requirements of SOI structure Si / SiO2 / Si materials. [0004] (2) Due to the inherent angle between the (111) crystal plane and the (100) crystal plane in KOH anisotropic etching, the opening of the TSV via hole will increase as the etching depth increases, making this type of "inverted ladder" The "type structure TSV through hole occupie...

AI Technical Summary

Problems solved by technology

[0003] (1) The above-mentioned interconnection structures are all implemented on single crystal silicon wafers, and the etching materials are all silicon, which cannot meet the requirements of etching of SOI structure Si / SiO2 / Si materials

[0004] (2) Due to the inherent angle between the (111) crystal plane and the (100) crystal plane in KOH anisotropic etching, the opening of the TSV via hole will increase as the etching depth increases, making this type of "inverted ladder" "Type structure TSV through holes occupy too much area, poor economy, and the process uses KOH as auxiliary liquid, which is easy to introduce K+ pollution, which will cause K+ pollution to the CMOS process line

Due to the existence of the "Notching" structure, if the above-mentioned interconnection structure is adopted, it will be difficult to carry out the subsequent insulation of the sidewall of the via, the production of the barrier layer / seed layer, and the metallization of the via, and it will cause increased leakage and reduced withstand voltage, which will affect SOI. Stereo Integrated Device Performance and Reliability

Images