Three-dimensional integrated power thin film hybrid integrated circuit integration method

Abstract

The invention discloses an integration method of a three-dimensional integrated power thin film hybrid integrated circuit. In the method, a convex ceramic substrate is used instead of a planar ceramic substrate, and chip and chip components are simultaneously carried out on the horizontal surface of the convex ceramic substrate and the two sides of the convex part. Integration of devices; use layered integral chemical plating and electroplating methods to form nickel-chromium-gold thin films, and then use photolithography and selective etching methods to form the required conduction band film or stop band film according to the product design pattern; use laser After the resistance is adjusted, the required film substrate is obtained; the two sides are connected through through holes and metallized filling; the substrate is mounted on the tube base by eutectic welding or paste bonding, and finally the film substrate is used In the way of hybrid integration, more than one semiconductor chip or other chip components are integrated on the convex ceramic substrate, and the wire bonding of the semiconductor chip is completed. The device produced by the method has a wide range of applications, and is especially suitable for the field of miniaturization and high reliability of equipment systems.

Description

technical field [0001] The present invention relates to a hybrid integrated circuit, further to a thin film hybrid integrated circuit, especially to a three-dimensional integrated power thin film hybrid integrated circuit. Background technique [0002] In the original hybrid circuit integration technology, two-dimensional planar integration technology or three-dimensional vertical stacked chip technology is used on the hybrid integration surface of the ceramic substrate, and semiconductor chips and other chip components are directly mounted on the film substrate, and then bonded. Wire bonding (gold wire or silicon-aluminum wire) is used to complete the entire electrical connection, and finally the tube base and tube cap are sealed in a specific atmosphere. [0003] The main problem of the original technology is: due to the use of two-dimensional planar integration technology, semiconductor chips and other chip components are mounted on the ceramic substrate in the direction ...

AI Technical Summary

Problems solved by technology

[0003] The main problem of the original technology is: due to the use of two-dimensional planar integration technology, semiconductor chips and other chip components are mounted on the ceramic substrate in the direction of the largest surface, and the wire bonding between the chip and the substrate is from one solder point to the other. There needs to be a certain span between a solder joint, and the necessary thin film resistors, thin film capacitors, thin film inductors, etc. need to be made on the substrate according to the requirements of the specific circuit. Therefore, the number of chips mounted on the surface of the substrate is limited, and the chip integration efficiency Affected by the substrate area, it is difficult to increase the chip integration level

However, these patents have nothing to do with the present invention, and there is currently no application for three-dimensional integrated power thin film hybrid integrated circuits

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