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Metal interconnect structure and fabrication method thereof

A technology of metal interconnection structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., and can solve aluminum-electrical migration, unequal, aluminum-silicon Schottky barrier height instability, etc. problem, achieve the effect of enhancing electrical performance and reducing resistance

Active Publication Date: 2016-08-10
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] Among them, aluminum has the following disadvantages: the contact resistance of aluminum-silicon is easy to be too large, solid-solid diffusion occurs between aluminum and silicon, electromigration of aluminum, aluminum cannot withstand high temperature treatment, and the height of aluminum-silicon Schottky barrier is not high. stable etc.
However, seedless electroplating also brings new challenges to the copper electroplating process. The difference in structure between ruthenium and copper makes copper electroplating on ruthenium not equivalent to copper electroplating. There are still many challenges in the interface growth and deposition modes. research question

Method used

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  • Metal interconnect structure and fabrication method thereof
  • Metal interconnect structure and fabrication method thereof
  • Metal interconnect structure and fabrication method thereof

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Embodiment 1

[0061] This embodiment takes a single contact hole as an example, its structure is as follows figure 1 As shown, the contact hole is formed in the interlayer dielectric layer 11 on the semiconductor substrate 10 . The semiconductor substrate 10 may be, but not limited to, a silicon substrate. MOS field effect transistors are formed on the silicon substrate, and other semiconductor device structures may also be formed. The source region 1 and the drain region 2 of the MOS field effect transistor are formed in the semiconductor substrate 10 , and the gate 3 thereof is formed on the surface of the semiconductor substrate 10 between the source region 1 and the drain region 2 . In this embodiment, the contact hole is formed on the source region 1 and the drain region 2 as an example. That is, through holes are respectively formed in the interlayer dielectric 11 above the source region 1 or the drain region 2, and the through holes are filled with a metal material 15, and there is...

Embodiment 2

[0066] In this embodiment, the metal interconnection structure of the dual damascene structure is taken as an example, which is specifically as follows figure 2 As shown, the dual damascene structure is formed in the interlayer dielectric layer 11'. The interlayer dielectric layer 11 ′ may be an interlayer dielectric between the nth layer and the n+1th metal layer, where n is greater than or equal to 1. An opening in the shape of a dual damascene structure formed by a combination of a via hole in the lower nth interlayer dielectric layer and a trench in the upper n+1th interlayer dielectric layer is formed in the interlayer dielectric layer , wherein the metal material 15' is filled in the opening, the metal material 15' and the sidewalls on both sides of the dual damascene structure have gaps, and the surface of the metal material 15' and the gap are graphene layers 16'. The graphene layer 16' is a monoatomic layer or a polyatomic layer less than 10 atomic layers.

[0067...

Embodiment 3

[0071] image 3 It is a flow chart of an embodiment of the method for fabricating the metal interconnection structure of the present invention, Figure 4 to Figure 12 is a schematic cross-sectional view of the intermediate structure and the final structure formed according to the above process. The following combination image 3 and Figure 4 to Figure 12 The fabrication method of the metal interconnection structure of the present invention is described in detail.

[0072] Executing step S1: providing a semiconductor substrate;

[0073] Such as Figure 4 As shown, the semiconductor substrate 100 in this embodiment is but not limited to a silicon substrate. MOS field effect transistors or other semiconductor device structures may be formed on the semiconductor substrate 100 . The source region 11 and the drain region 22 of the MOS field effect transistor are formed in the semiconductor substrate 100 , and the gate 33 thereof is formed on the surface of the semiconductor s...

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Abstract

The invention provides a metal interconnection structure and a manufacturing method thereof. The metal interconnection structure comprises an interlevel dielectric layer, an opening, metal material and graphene layers. The opening is formed in the interlevel dielectric layer, a through hole or a groove is filled with the metal material, and the graphene layers are formed on the surface of the metal material and between the metal material and the interlevel dielectric layer. The manufacturing method including the steps of providing a semiconductor substrate, forming a sacrificial layer on the semiconductor substrate, forming the opening in the sacrificial layer, filling the opening with the metal material, removing the sacrificial layer to expose side walls of the metal material, and forming the graphene layers on the surface of the metal material. According to the metal interconnection structure and the manufacturing method thereof, by utilizing the characteristic that graphene can grow adhered to the metal material such as copper and nickel, the graphene is formed on the surface of the metal material in the metal interconnection structure as a part of metal interconnection, and therefore resistance of the metal interconnection structure is greatly reduced.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a metal interconnection structure and a manufacturing method thereof. Background technique [0002] The metal interconnection process is a process of depositing a metal film on an integrated circuit and forming wiring through photolithography and etching technology to interconnect mutually isolated components into a required circuit according to certain requirements. [0003] The general requirements for metal materials or other conductive materials used in metal interconnection processes are: low resistivity, good low-ohmic contact with the electrodes of the device; good adhesion to the silicon dioxide layer; easy deposition and photolithography to form wiring and the like. [0004] The metal materials commonly used in the metal interconnection process are: aluminum, copper, tungsten, etc. [0005] Among them, aluminum has the following disadvantages: the contact resist...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/532H01L21/768
Inventor 张海洋符雅丽
Owner SEMICON MFG INT (SHANGHAI) CORP
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