Metal interconnect structure and fabrication method thereof
A technology of metal interconnection structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., and can solve aluminum-electrical migration, unequal, aluminum-silicon Schottky barrier height instability, etc. problem, achieve the effect of enhancing electrical performance and reducing resistance
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Embodiment 1
[0061] This embodiment takes a single contact hole as an example, its structure is as follows figure 1 As shown, the contact hole is formed in the interlayer dielectric layer 11 on the semiconductor substrate 10 . The semiconductor substrate 10 may be, but not limited to, a silicon substrate. MOS field effect transistors are formed on the silicon substrate, and other semiconductor device structures may also be formed. The source region 1 and the drain region 2 of the MOS field effect transistor are formed in the semiconductor substrate 10 , and the gate 3 thereof is formed on the surface of the semiconductor substrate 10 between the source region 1 and the drain region 2 . In this embodiment, the contact hole is formed on the source region 1 and the drain region 2 as an example. That is, through holes are respectively formed in the interlayer dielectric 11 above the source region 1 or the drain region 2, and the through holes are filled with a metal material 15, and there is...
Embodiment 2
[0066] In this embodiment, the metal interconnection structure of the dual damascene structure is taken as an example, which is specifically as follows figure 2 As shown, the dual damascene structure is formed in the interlayer dielectric layer 11'. The interlayer dielectric layer 11 ′ may be an interlayer dielectric between the nth layer and the n+1th metal layer, where n is greater than or equal to 1. An opening in the shape of a dual damascene structure formed by a combination of a via hole in the lower nth interlayer dielectric layer and a trench in the upper n+1th interlayer dielectric layer is formed in the interlayer dielectric layer , wherein the metal material 15' is filled in the opening, the metal material 15' and the sidewalls on both sides of the dual damascene structure have gaps, and the surface of the metal material 15' and the gap are graphene layers 16'. The graphene layer 16' is a monoatomic layer or a polyatomic layer less than 10 atomic layers.
[0067...
Embodiment 3
[0071] image 3 It is a flow chart of an embodiment of the method for fabricating the metal interconnection structure of the present invention, Figure 4 to Figure 12 is a schematic cross-sectional view of the intermediate structure and the final structure formed according to the above process. The following combination image 3 and Figure 4 to Figure 12 The fabrication method of the metal interconnection structure of the present invention is described in detail.
[0072] Executing step S1: providing a semiconductor substrate;
[0073] Such as Figure 4 As shown, the semiconductor substrate 100 in this embodiment is but not limited to a silicon substrate. MOS field effect transistors or other semiconductor device structures may be formed on the semiconductor substrate 100 . The source region 11 and the drain region 22 of the MOS field effect transistor are formed in the semiconductor substrate 100 , and the gate 33 thereof is formed on the surface of the semiconductor s...
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Abstract
Description
Claims
Application Information
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