Preparation method of trench gate in trench MOS device

Abstract

The invention discloses a preparation method of a trench gate in a trench MOS device. The preparation method of the trench gate in the trench MOS device is characterized in that the thickness of a gate oxidation film at the bottom of a trench is larger than the thickness of a gate oxidation film at the sidewall of the trench. The preparation method includes the following steps that: 1, a trench is formed on a silicon wafer through photo-etching and etching, and a trench gate is required to be produced on the silicon wafer; 2, a first gate oxidation film is grown; 3, spin coating of photoresist is performed; 4, the photoresist is removed partially, and part of the photoresist, which is located at the bottom of the trench, is reserved; 5, a part of the first gate oxidation film, which is located at the sidewall of the trench and the surface of the silicon wafer, is removed, and a part of the first gate oxidation film, which is located at the bottom of the trench, is reserved, and part of the photoresist, which is located at the bottom of the trench, is removed; 6, a second gate oxidation film is grown; polycrystalline silicon is filled; 8, planarization is performed on the polycrystalline silicon through etch-back or chemical mechanical lapping, and the final trench gate can be formed. With the preparation method of the trench gate in the trench MOS device of the invention adopted, parasitic capacitance between a gate and a drain can be reduced, and the switching speed of the trench MOS device can be improved, and switching loss can be decreased, and at the same time, the problem of proneness to electric breakdown at the bottom of the trench of the trench MOS device can be solved.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process, in particular to a method for preparing a trench gate in a trench MOS device. Background technique [0002] In traditional planar MOS (Metal Oxide Semiconductor) devices, the source, gate and drain of the MOS transistors are all located on the horizontal plane of the silicon wafer, which not only occupies a large area, but also has a large on-resistance and power consumption. , unable to meet the requirements of miniaturization and low power consumption of power devices. The trench MOS device cleverly forms the gate of the transistor in a groove perpendicular to the surface of the silicon wafer, so that the conduction channel is transferred to the longitudinal direction of the silicon wafer. This has three advantages: (1) Reduce the device area , to further increase the device integration density, (2) effectively reduce the on-resistance and power consumption, (3) basic...

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Problems solved by technology

In the above method, the thickness of the gate oxide film at the bottom of the trench is basically the same as the thickness of the gate oxide film on the sidewall of the trench, so the parasitic capacitance between the gate and the drain is large, which affects the switching speed of the trench MOS device ; At the same time, since the curvature at the corner 700 at the bottom of the trench is very large, the electric field is easy to concentrate, so electrical breakdown is most likely to occur at this part and affect the overall breakdown voltage of the device

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