Semiconductor device manufacturing method, semiconductor device and electronic device

Abstract

The invention provides a manufacturing method for a semiconductor device. The manufacturing method comprises: a semiconductor substrate is provided and a groove for forming a through silicon via is formed in the semiconductor substrate; a protection layer that covers the side wall and the bottom of the groove and is used for absorbing a swelling stress is formed; at least one transition layer is formed on the protection layer; and the groove is filled by metallic copper, wherein the transition layer employs a metal material and the thermal expansion coefficient of the transition layer is smaller than that of the copper. According to the manufacturing method, the metal material having the small thermal expansion coefficient is added between the silicon and cooper during the through silicon via forming process to form the transition layer between the Si / Cu, so that the thermal mismatching between the two kinds of materials is reduced; the thermal expansion coefficient is increased gradually from the transition layer to the metallic copper layer, thereby reducing the thermal mismatching among all materials at all layers effectively and thus avoiding layering or copper layer protrusion.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device, a semiconductor device and an electronic device. Background technique [0002] In the field of semiconductor technology, through-silicon via (TSV) technology is the key to realizing vertical interconnection. The 3D integration method using TSV technology can improve the integration level of devices, data exchange speed and signal speed, reduce interconnection length, reduce power consumption and improve In terms of performance such as input / output density, it is also possible to realize multi-functional integrated packaging such as memory, dedicated IC, and processing area in one package. [0003] In wafers with through-silicon vias (TSVs), metal copper is usually used to fill the TSVs for interconnection. However, due to the large difference between the physical properties of copper and silicon, the use of large v...

AI Technical Summary

Problems solved by technology

figure 2 It shows the problem of copper bumps in the TSV via hole, the main reason is that the copper volume expands during the heating process, the volume of copper in the TSV hole is very large, resulting in a large amount of expansion, and the protruding part affects the aluminum above it Pad and first metal layer

[0004] In production, such problems are usually alleviated by adjusting the ingredients (recipe) in the process, and the yield and reliability are improved. However, the fundamental reasons such as copper / silicon differences and excessive copper volume still exist. Therefore, these problems can still happen

In addition, there are currently methods to alleviate this problem by thickening the SiO2 layer or adding some plastic materials, such as benzocyclobutene (BCB), etc. to absorb the internal stress of copper, but in the smaller TSV structure, adding these non- Conductive materials may have some influence on their ability to conduct electricity

Images