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Semiconductor substrate, three-dimensional package chip and through-silicon via packaging method

A packaging method and a technology of through-silicon vias, which are applied in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve problems such as inconsistent thermal expansion coefficients, time-consuming manufacturing processes, and chip failures, etc., to improve the quality of finished products efficiency, prolong life, and simplify the manufacturing process

Inactive Publication Date: 2017-05-24
HUAZHONG UNIV OF SCI & TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This method has the following disadvantages: 1. While filling the TSV with electroplating, conductive materials are also growing on the substrate surface around the TSV; after the filling is completed, a thick layer of conductive material will grow on the TSV hole and its surroundings, which needs to be carried out later. Long time CMP polishing removal, making the manufacturing process time-consuming and costly
2. Since the TSV hole is filled with conductive material, and the coefficient of thermal expansion (CTE) of the conductive material and the substrate is inconsistent, the substrate is prone to cracks at the TSV under thermal cycle and thermal shock conditions, resulting in chip failure

Method used

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  • Semiconductor substrate, three-dimensional package chip and through-silicon via packaging method
  • Semiconductor substrate, three-dimensional package chip and through-silicon via packaging method
  • Semiconductor substrate, three-dimensional package chip and through-silicon via packaging method

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Embodiment 1

[0035] The preparation method of the semiconductor substrate of embodiment 1 is as image 3As shown, due to the improvement of the TSV packaging method, the process flow includes drilling, sequentially making insulating layers, photolithography, sequentially sputtering to make barrier layers, conductive materials and circuit layers, and stripping. Compared with the prior art, polishing is omitted process.

[0036] Such as Figure 4a As shown, it is a schematic diagram of the TSV (through-silicon via) pad array in Example 1. The size of the pad is 140 μm×140 μm, and each pad is distributed with a 7×7 square array of TSVs, and the diameter of each TSV hole is 10 μm. The pitch is 20 μm, the depth is 100 μm, and the thickness of the semiconductor base substrate where the TSV hole is located is 100 μm, such as Figure 4b shown. Each TSV is filled with copper rings by double-sided magnetron sputtering. Magnetron sputtering FHR equipment is used. The vacuum degree is 2E-7mbar, the...

Embodiment 2

[0038] For semiconductor substrates that are not suitable for thinning, due to the large depth of the semiconductor substrate and the limited TSV aspect ratio (generally not exceeding 10:1), the TSV aperture is usually large. The thickness of the semiconductor substrate in this embodiment is 600 μm, and the TSV aperture is 60 μm, such as Figure 5a shown. Due to the limitations of sputtering itself (cost and equipment performance), the thickness of the sputtered metal layer generally does not exceed 2 μm, and if sputtering is still used for copper filling at this time, the TSV copper filling rate may be less than 12.9%, resulting in semiconductor The electrical conductivity of the substrate is insufficient.

[0039] Therefore, for the preparation of this kind of chip, the filling method of electroplating is still used. For the TSV with a pore size of 60 μm, if electroplating is used for filling, since the copper layer is also grown on the surface of the chip when the TSV is e...

Embodiment 9

[0044] Filling TSVs by evaporation is similar to sputtering. The difference is that the sidewall attachment efficiency of evaporation is not as high as that of sputtering, and it is only suitable for filling TSVs with low aspect ratios. However, the advantage of evaporation is that it can achieve larger batches of processing technology. The equipment can realize the processing of multiple wafers at a time, and the cost is relatively low. For example, the diameter of TSV is 20 μm, the depth is 100 μm, and the aspect ratio is only 5:1. At this time, the electron beam evaporation process can be used to evaporate the copper layer on both sides in large quantities, using the COOKE electron beam evaporation table, and the evaporation rate is 20A / s , the pre-evaporation power is 45%, the evaporation power is 60%, and each side is evaporated for 3 hours to form a copper layer with a thickness of 2 μm, so that the thickness of the copper layer on the side wall of the TSV is 4 μm, and th...

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Abstract

The invention discloses a semiconductor substrate, a three-dimensional package chip and a through-silicon via packaging method. The semiconductor substrate has a through-silicon via running through the semiconductor substrate; the internal surface of the through-silicon via is circumferentially deposited by a conductive material, the thickness of which is smaller than 2 mum; the volume fraction of the conductive material in the through-silicon via is 5 vol.%-95 vol.%; and the center of the through-silicon via has a gap running through the through-silicon via. Only the internal surface of the through-silicon via is circumferentially deposited by the conductive material, and the center of the through-silicon via in the semiconductor substrate still has a certain gap, so that the prepared three-dimensional package chip does not deform easily under hot and cold environment, yield is improved, and the service life of the three-dimensional package chip is prolonged.

Description

technical field [0001] The invention belongs to the technical field of semiconductor manufacturing, and more specifically relates to a packaging method for a semiconductor substrate, a three-dimensional packaging chip and a through-silicon via. Background technique [0002] Through-Silicon-Via technology (Through-Silicon-Via, TSV) is the main method to realize the interconnection between chips by making vertical conduction between chips and wafers. important role in integrated circuits. [0003] The prior art TSV technology (Microelectronic Engineering, Volume 150, 25January 2016, Pages 39–42) such as figure 1 As shown: including drilling holes on the substrate, making insulating layers, barrier layers, and seed layers, and then using electroplating to generate conductive materials in the TSV holes, filling all the TSV holes, and then making a mask layer by photolithography. The surface circuit layer and pads are produced by sputtering, and finally the chip is packaged aft...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/13H01L23/31H01L23/538H01L21/56H01L21/768
CPCH01L21/56H01L21/76879H01L23/13H01L23/31H01L23/538H01L2224/16225
Inventor 李操费鹏刘胜
Owner HUAZHONG UNIV OF SCI & TECH
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