A kind of integrated SBD silicon carbide trench mosfets and its preparation method

A technology of silicon carbide trench and silicon carbide substrate, which is applied to the structure and preparation of trench metal-oxide-semiconductor field effect transistors, and can solve the problem of excessive electric field

Active Publication Date: 2021-08-20
INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a silicon carbide trench MOSFETs integrated with SBDs, so as to alleviate the problem of excessive electric field of the gate dielectric in silicon carbide trench MOSFETs in the prior art, and at the same time greatly improve the power source when MOSFETs work in reverse. Leakage current density can effectively suppress the electrical stress of parasitic PN diodes inside SiC trench MOSFETs, thereby improving chip integration and functionality, reducing the total chip area of ​​SiC MOSFETs and SBDs and the cost of the entire power module

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A kind of integrated SBD silicon carbide trench mosfets and its preparation method
  • A kind of integrated SBD silicon carbide trench mosfets and its preparation method
  • A kind of integrated SBD silicon carbide trench mosfets and its preparation method

Examples

Experimental program
Comparison scheme
Effect test

preparation example Construction

[0109] figure 2 It is a schematic diagram of the steps of the preparation method, such as figure 2 Shown, described preparation method comprises:

[0110] Step A: making a silicon carbide epitaxial wafer substrate; including, sequentially growing an n+ type buffer layer 20, an n-drift layer 30 and an n-type current transport layer 40 on an n++ type silicon carbide substrate 10 from bottom to top, as image 3 shown;

[0111] Step B: Doping the active region in the n-type current transport layer 40, including:

[0112] method 1)

[0113] Sub-step B1: Deposit an implantation mask on the n-type current transport layer 40, pattern it by photolithography, and use doping methods such as ion implantation to form a top-down p-type trench in the n-type current transport layer 40 channel layer 41 and p+ type shielding layer 42, such as Figure 4 shown;

[0114] In the sub-step B1, the doping concentration range of the p-type channel layer 41 is 1×10 16 cm -3 ~1×10 18 cm -3 , ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
Login to view more

Abstract

The invention provides a silicon carbide trench MOSFETs integrated with SBDs and a preparation method thereof. The side wall gate electrode contact of the MOSFETs is located on the side wall of the main trench, and the source electrode metal contact is formed at the bottom of the trench, and a Schottky metal contact is integrated. When the first quadrant is forward-conducting, electrons flow through the side of the trench from bottom to top The wall inversion layer forms a reverse conduction channel different from traditional trench MOSFETs; when the third quadrant is forward conduction, the Schottky diode is first to conduct, effectively suppressing the conduction of parasitic PN diodes in the body; reverse blocking When , the p-type shielding layer at the bottom of the trench effectively shields the high electric field of the device body region, so that the electric field of the device gate dielectric and the Schottky contact electric field are greatly reduced, and the avalanche occurs at the PN junction of the device body region. The silicon carbide trench MOSFETs integrated with SBDs have a lower total chip area, while satisfying good first and third quadrant conduction characteristics and reverse blocking capabilities, and the static and dynamic operating reliability of the device are improved. .

Description

technical field [0001] The invention relates to a structure of a trench type metal-oxide-semiconductor field-effect transistor (MOSFETs) integrating a silicon carbide Schottky diode (SBD) and a preparation method thereof. Background technique [0002] In the field of power electronic conversion, reducing the loss of power devices and the area of ​​integrated chips can significantly improve the overall efficiency of the system. The critical breakdown electric field of silicon carbide is 10 times that of Si, and it is currently the most mature wide bandgap power semiconductor device. SiC trench MOSFETs have higher cell integration and non-polar surface carrier mobility, which can further reduce the chip area and on-state resistance of SiC-based power devices. This makes SiC trench MOSFETs attract more and more attention, especially for power electronics applications such as electric vehicles, charging piles, uninterruptible power supplies and smart grids. [0003] However, w...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/06H01L29/423H01L29/45H01L29/78H01L21/336H01L21/28
CPCH01L29/0684H01L29/401H01L29/4236H01L29/42364H01L29/45H01L29/66068H01L29/7827
Inventor 申占伟张峰温正欣赵万顺王雷闫果果刘兴昉孙国胜曾一平
Owner INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products