Manufacturing method of fan-out chip interconnection

Abstract

The invention discloses a fan-out chip interconnection manufacturing method, which comprises the steps: coating the surface of a fan-out chip with a photoresist or a passivation layer, and opening thephotoresist or the passivation layer covering the PAD region of the fan-out chip to expose the PAD of the fan-out chip; manufacturing an insulating layer on the surface of the fan-out chip, then manufacturing a seed layer above the insulating layer, then coating with an electroplating photoresist, electroplating with a metal to make RDL, then removing the photoresist, and then removing the seed layer; and connecting the other end of the RDL with the internal bonding pad, and remanufacturing an external bonding pad on the internal bonding pad. According to the invention, the size of the remanufactured external bonding pad is increased, and the distance between the bonding pads is increased; and the area and the position of the chip PAD are redefined, so that the difficulty of interconnection between the embedded fan-out chip PAD and the wafer-level RDL can be greatly reduced, the problems of open circuit and short circuit are reduced, and the reliability of the process is improved.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a method for fabricating fan-out chip interconnections. Background technique [0002] Millimeter-wave radio frequency technology is developing rapidly in the semiconductor industry. It is widely used in high-speed data communications, automotive radar, airborne missile tracking systems, and spatial spectral detection and imaging. It is expected that the market will reach 1.1 billion US dollars in 2018 and become an emerging industry. New applications put forward new requirements for the electrical performance, compact structure and system reliability of the product. For the wireless transmitting and receiving system, it cannot be integrated into the same chip (SOC), so it is necessary to integrate different chips including radio frequency units. , filters, power amplifiers, etc. are integrated into an independent system to realize the functions of transmitting and receiving signals....

AI Technical Summary

Problems solved by technology

[0003] The traditional packaging technology installs various functional chips and passive devices on the substrate, which occupies a large area and has poor reliability, which cannot meet the trend of miniaturization of packaging systems. However, the three-dimensional heterogeneous packaging technology based on standard silicon technology (system-level Packaging SIP) uses TSV technology (Through Silicon Via, referred to as TSV, through-silicon via technology) and cavity structure to integrate chips with different substrates and different functions, which can realize chip stacking and interconnection in a small area, greatly Reducing the area of ​​functional parts and increasing their reliability is becoming more and more the direction of future development of the industry

[0004] However, due to the high complexity of the embedded chip process, the chip tends to be shifted inside the cavity. If there is a lot of shift, and the exposure of the subsequent wafer-level RDL (redistribution layer) process will also shift, Then there may be a short circuit or open circuit problem between the chip PAD (silicon chip pin) and the RDL line; also as the number of PADs in the subsequent chip increases, the gap between the PAD and the PAD becomes smaller and smaller, which is not conducive to Alignment for Embedded Wafer-Level Fan-Out Packaging

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