Epitaxy method for reducing stacking fault defects of epitaxial wafers and application of epitaxy method

Abstract

The invention discloses an epitaxial method for reducing stacking fault defects of epitaxial wafers. The epitaxial method comprises the following steps: S1, placing a substrate at a growth position ina reaction chamber; S2, introducing hydrogen into the reaction chamber, raising the temperature, and performing etching for 10-20 minutes in a hydrogen atmosphere; S3, introducing ethylene and trichlorosilane gas into the reaction chamber until the C / Si ratio is 0.9-1.2, and growing a first epitaxial buffer layer at a low speed; S4, continuously introducing ethylene and trichlorosilane gas into the reaction chamber until the C / Si ratio is 0.6-0.9, and growing a second epitaxial buffer layer at a low speed; S5, stopping introducing ethylene and trichlorosilane into the reaction chamber, cooling, and etching for 4-10 minutes in a hydrogen atmosphere; S6, gradually increasing the flow of ethylene and trichlorosilane until the C / Si ratio is 1.0-1.2, and growing an epitaxial layer at a high speed to form an epitaxial wafer; S7, reducing the temperature of the reaction chamber, and taking out the epitaxial wafer for detecting, cleaning and packaging.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an epitaxial method for reducing stacking fault defects of epitaxial wafers and an application thereof. Background technique [0002] Epitaxy is one of the semiconductor processes. The epitaxy process refers to the process of growing a single crystal thin film on a single crystal substrate according to the crystal direction of the substrate. The new single crystal layer is called an epitaxial layer, and the substrate with an epitaxial layer called epitaxial wafers. [0003] SiC is a wide-bandgap semiconductor material with excellent physical and electrical properties, such as high breakdown electric field, high packet and electron mobility, and high thermal conductivity. This makes it one of the mainstream materials for preparing high-temperature, high-voltage, high-frequency, high-power and low-loss electronic devices. The existing 4H-SiC epitaxial layer epitaxial proce...

AI Technical Summary

Problems solved by technology

The existing 4H-SiC epitaxial layer epitaxial process method is mainly aimed at a specific single-wafer vertical epitaxial reactor, such as a 4-inch 4H-SiC epitaxial process. Due to different sizes of epitaxial wafers, the tray structure and size used and the gas inlet device The temperature field distribution of the wafer and the flow field distribution of the reaction gas will have certain differences during the growth. Therefore, the existing 4H-SiC epitaxial layer epitaxy process is not suitable for horizontal, etc. epitaxial reactor

[0004] At present, the industry mainly grows high-quality 4H-SiC epitaxial wafers with different doping concentrations and thicknesses through homoepitaxial technology based on chemical vapor deposition, and then prepares electronic devices that meet different electrical properties. However, in 4H-SiC epitaxy During the growth process, there will be a plane defect in which the stacking sequence of some atomic layers is inconsistent with the ideal stacking sequence, which is called stacking fault (SF and SSF). Usually, the stacking fault density of epitaxial wafers grown by conventional epitaxial processes Larger (2 ~ 5cm -2 ), where some of the stacking faults nucleate in the epitaxial layer (related to the stress in the epitaxial layer), while the other part of the stacking faults nucleate in the interface between the epitaxial layer and the substrate (with the substrate on the The stacking fault defect will not only increase the reverse leakage current of the 4H-SiC diode, but also reduce the breakdown voltage, seriously affecting the performance of the 4H-SiC electronic device

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