Nanowire and electronic device
A technology of electronic devices and nanowires, applied in the field of nanowires, can solve the problems such as the inability to realize the expectations of nanoelectronic devices and the inability to utilize the quantum potential.
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Embodiment 1
[0040] A thin gold layer of 0.5-3 nm is provided on a silicon semiconductor substrate with an oxidized surface. The semiconductor substrate was placed in a quartz tube at the first end of the reaction furnace. A fixed InP target is placed at the second end of the reaction furnace so that evaporated InP can be carried by the gas flow along the quartz tube to the substrate. Evacuate the reaction furnace to below 10Pa. Then, set the pressure to 3×10 4 Pa, Ar flow rate is 100-300 sccm. The reaction furnace was heated to 500°C. This cleaves the gold layer and forms nanoscale clusters. At this temperature, the target was melted with an ArF laser having a wavelength of 193 nm. This leads to the growth of InP nanowires 10 using Au whiskers as catalysts. The obtained nanowires include a first zone 1 , a second zone 2 and a third zone 3 .
[0041] After having grown a first zone 1 with nanowires 10 of 200 nm, typically 100-1000 nm, and 10 nm in diameter, the temperature is increa...
Embodiment 2
[0043] In the same manner as in Example 1, Au whiskers were formed on the substrate. at 3cm 3 STP / min for silane and 18cm 3 Silicon nanowires were grown by chemical vapor deposition at 450° C. in an atmosphere of 100 ppm phosphine under He at STP / min. Thus after the nanowires of 100-1000 nm have been grown, the temperature is raised to 500°C. This results in more Si being dissolved into the Au whiskers, whereby the volume and diameter of the whiskers increases. The result is that the nanowires have a local width extension of 15-50 nm, thus forming the second region. After 10-60 seconds, the temperature was again lowered to 450°C. Nanowires are further grown at this temperature until nanowires with a total length of 200-2000 nm are produced.
Embodiment 3
[0045] A bilayer photosensitive layer consisting of a 400 nm thick lower layer of strongly baked Shipley AXS1813 and an 80 nm thick upper layer of e-beam resist was provided on a semiconductor substrate. Using radiation (electron beam, 100kV, 100μC / cm 2 ) to pattern the two-layer photosensitive layer, thereby defining isolation regions. These isolation regions have a diameter of 50×50 nm and are 1.0 μm apart from each other. The upper layer was developed and then immersed in isopropanol. Then, in the 0.3Pa oxygen plasma etching step, at 0.07W / cm 2 The low RF power density and -170V DC bias anisotropically transform the pattern from the upper layer to the lower layer.
[0046] Then, the semiconductor substrate is etched in a direction substantially perpendicular to the surface. This etching is performed by dry etching with inductively coupled plasma (ICP), wherein etching steps and passivation steps are performed alternately. RF control (13.56MHz) processing. The etching ...
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