Porous film, composition and manufacturing method, interlayer dielectric film, and semiconductor device

a technology of dielectric film and porous film, which is applied in the direction of plastic/resin/waxes insulators, basic electric elements, coatings, etc., can solve the problems of increasing the cost affecting the performance of the first porous film forming method, and affecting the interconnection delay time, etc., to achieve the effect of reducing parasitic capacitance, reducing the amount of porous film forming method, and maintaining mechanical strength

US20060220253A1Inactive Publication Date: 2006-10-05HAMADA YOSHITAKA +3
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Patent Information

Authority / Receiving Office
US · United States
Patent Type
Applications(United States)
Current Assignee / Owner
Publication Date
2006-10-05
Estimated Expiration
Not applicable · inactive patent

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Abstract

A porous film-forming composition comprising (A) a curable silicone resin having a Mn of at least 100, (B) a micelle-forming surfactant, and (C) a compound which generates an acid upon pyrolysis remains stable during storage. The composition is coated and heat treated to form a porous film which has flatness, uniformity, a low dielectric constant and a high mechanical strength so that it is best suited as an interlayer dielectric film in the fabrication of semiconductor devices.
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Description

[0001] This application is a Divisional of co-pending Application No. 10 / 808,361, filed on Mar. 25, 2004, the entire contents of which are hereby incorporated by reference and for which priority is claimed under 35 U.S.C. § 120.BACKGROUND OF THE INVENTION

[0002] 1. Technical Field

[0003] This invention relates to a composition for forming a porous film having improved dielectric properties, adhesion, coating uniformity, mechanical strength, and minimized moisture absorption, a method of manufacturing a porous film, a porous film, an interlayer dielectric film, and a semiconductor device having a porous film built therein.

[0004] 2. Background Art

[0005] In the progress of semiconductor integrated circuits toward higher integration, an increase of interconnect delay time caused by an increase of wiring capacitance which is a parasitic capacitance between metal wires becomes a barrier in enhancing the performance of semiconductor integrated circuits. The interconnect delay time, also ...

Examples

preparation example 1

[0084] In a 50-ml flask, 15.22 g of tetramethoxysilane was hydrolyzed with 7.20 g of water (corresponding to twice the equivalent for hydrolysis) and 0.1 ml of 2N hydrochloric acid, yielding a silica precursor with Mw=1,450.

preparation example 2

[0085] In a 50-ml flask, a mixture of 11.42 g of tetramethoxysilane and 3.41 g of methyltrimethoxysilane was hydrolyzed with 6.75 g of water (corresponding to twice the equivalent for hydrolysis) and 0.1 ml of 2N hydrochloric acid, yielding a silica precursor with Mw=2,250.

preparation examples 3-7

[0086] Various surfactants, shown in Table 1, were added to the silica precursor solutions of Preparation Examples 1 and 2, which were diluted with water to form solutions having a solids (NV) concentration of 20%.

[0087] Note that Preparation Example is abbreviated as PE.

TABLE 1ResinC18H37NMe3ClC16H33NMe3OHC16H33NMe3OAcC12H25O(EO)9HWaterPreparationPreparation3.4 g14.8 gExample 3Example 1PreparationPreparation3.0 g14.8 gExample 4Example 1PreparationPreparation3.3 g14.8 gExample 5Example 1PreparationPreparation2.9 g14.8 gExample 6Example 1PreparationPreparation3.4 g14.8 gExample 7Example 2

Note:

Me = methyl,

Ac = acyl,

EO = ethylene oxide