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Silicon wafer, method for manufacturing the same and method for heat-treating the same

A technology of heat treatment method and manufacturing method, which is applied in the directions of post-processing, post-processing details, chemical instruments and methods, etc., can solve the problems of easy slippage, increase thermal stress, etc., so as to help yield and improve thermal strength. , low cost effect

Active Publication Date: 2010-02-03
GLOBALWAFERS JAPAN
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0053] However, in the case of such rapid cooling, the thermal stress caused by the temperature distribution in the wafer surface increases, and there is a problem that slippage is likely to occur.

Method used

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  • Silicon wafer, method for manufacturing the same and method for heat-treating the same
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  • Silicon wafer, method for manufacturing the same and method for heat-treating the same

Examples

Experimental program
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Effect test

no. 1 approach

[0126] figure 1 It is a cross-sectional view schematically showing an example of an RTP device used in the method of manufacturing a silicon wafer of the present invention.

[0127] Such as figure 1 As shown, the RTP apparatus 10 used in the method of manufacturing a silicon wafer of the present invention includes: a reaction tube 20 having an atmospheric gas inlet 20a and an atmospheric gas discharge port 20b; The reaction space 25 in the reaction tube 20 supports the wafer support part 40 of the wafer W. The wafer support unit 40 includes an annular susceptor 40a that directly supports the wafer W, and a stage 40b that supports the susceptor 40a. The reaction tube 20 is made of, for example, quartz. The lamp 30 is constituted by, for example, a halogen lamp. The receptor 40a is made of silicon, for example. The stage 40b is made of quartz, for example.

[0128] in use as figure 1 When the shown RTP apparatus 10 performs rapid heating and rapid cooling heat treatment (...

Embodiment 1

[0176] The P-type, crystal plane orientation (001), solid dissolved oxygen concentration [Oi] was 1.2×10 produced by the CZ method. 18 atom / cm 3 (calculated value based on the conversion factor of Old ASTM), a single crystal silicon block with an impedance of 23-25Ω / cm.

[0177] At this time, the silicon wafer covered with the silicon nitride film was put into the nitrogen doping process, and the average crystal pulling speed was adjusted to 1.2mm / min. The crystal pulling rate V and the rate gradient G in the direction of the crystal axis at 1300° C. are controlled, thereby performing crystal pulling while controlling V / G.

[0178] Then, the obtained monocrystalline silicon ingot was cut into wafers with a wire saw, and subjected to beveling, polishing, etching, and grinding to produce a silicon wafer with a diameter of 300 mm polished on both sides.

[0179] Then, several silicon wafers produced were sampled in the same group. The native defects on the device surface of th...

Embodiment 1-2

[0186] The P-type, crystal plane orientation (001), solid dissolved oxygen concentration [Oi] 1.0×10 was produced by the CZ method. 18 atom / cm 3 (calculated value based on the conversion factor of Old ASTM), impedance 28-30Ω / cm, and a silicon wafer with a diameter of 300 mm polished on both sides was produced by the same method as in Example 1-1.

[0187] Next, several silicon wafers were sampled in the same group. The native defects on the device surface of the sampled silicon wafer were observed by AFM (Atomic Force Microscopy). The maximum value of the size converted to the diameter of a sphere having the same volume as the observed native defect was determined. As a result, the maximum value of the COP measured in Example 1-2 was 100 nm.

[0188] Second, use such as figure 1 The shown RTP device 10 performs rapid heating and rapid cooling heat treatment on the silicon wafer produced above. In embodiment 1-2, in such as figure 2 In the temperature program shown, the ...

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Abstract

A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating / cooling thermal process at a maximum temperature (T1) of 1300 DEG C or more, but less than 1380 DEG C in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more, but less than 100%. The silicon wafer (10) according to the invention has, in a defect-free region (DZ layer) (12) including at least a device active region of the silicon wafer, a high oxygen concentration region (12) having a concentration of oxygen solid solution of 0.71018 atoms / cm3 or more and at the same time, the defect-free region contains interstitial silicon (14) in supersaturated state.

Description

technical field [0001] The invention relates to a silicon wafer used as a substrate of a semiconductor device and a method for manufacturing the silicon wafer. In addition, the present invention relates to a heat treatment method for applying a silicon wafer obtained by cutting a monocrystalline silicon block produced by the Czochralski method (hereinafter referred to as "CZ" method) to a semiconductor device. Background technique [0002] With the high integration of semiconductor devices in recent years, the quality requirements for silicon substrates used as their substrates have also become more stringent. In particular, it is strongly required to reduce native defects and have high gettering effect in the device active region of the silicon wafer. [0003] In native defects, for example, aggregates of supersaturated hole-type point defects called COP (crystallization-induced particles) and LSTD (laser scattering tomography defects) grow and become OSF (oxidation-induce...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): C30B33/02H01L21/02H01L21/322H01L21/324C30B29/06
Inventor 矶贝宏道仙田刚士丰田英二村山久美子泉妻宏治前田进鹿岛一日児荒木浩司青木竜彦须藤治生望月阳一郎小林昭彦符森林
Owner GLOBALWAFERS JAPAN
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