Electrically erasable programmable read-only memory (EEPROM)

A storage unit and capacitor technology, applied in electrical components, electric solid devices, circuits, etc., can solve problems such as unfavorable chip working field strength, information loss, wrong writing, etc., to improve data storage capabilities, improve data storage capabilities, The effect of operating voltage reduction

Active Publication Date: 2014-11-19
合肥矽景电子有限责任公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Existing EEPROM consumes a lot of power because its gate structure is a vertical stack structure composed of polysilicon control gate, coupling oxide layer, polysilicon floating gate and tunnel oxide layer. The problems brought by this structure are: 1. Make the EEPROM The working voltage of the chip is high, which is not conducive to reducing the working field strength of

Method used

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  • Electrically erasable programmable read-only memory (EEPROM)
  • Electrically erasable programmable read-only memory (EEPROM)
  • Electrically erasable programmable read-only memory (EEPROM)

Examples

Experimental program
Comparison scheme
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Example Embodiment

[0019] Example one

[0020] Such as figure 1 An EEPROM memory cell is shown, the semiconductor substrate is a P-type doped epitaxial silicon wafer 100, a PMOS capacitor 110, a polysilicon capacitor 120, an NMOS selector tube 130, and an NMOS read tube 140 are formed on the semiconductor substrate; The PMOS capacitor 110 includes: ion implantation on the p-type doped epitaxial silicon wafer 100 to form an n-well 112, a gate oxide layer 102a, a gate oxide layer 102b, a floating gate 122a placed on the gate oxide layer 102a, source and drain Zone one 114a, source and drain zone two 114b, a MOS capacitor contact hole 116a placed on the source and drain zone 114a and a MOS capacitor contact hole 116b placed on the source and drain zone two 114b, the floating gate 122a serves as a PMOS capacitor The first MOS capacitor contact hole 116a and the second MOS capacitor contact hole 116b are short-circuited for connection to the DL, and the source-drain region 114a and the source-drain reg...

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PUM

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Abstract

The present invention discloses an EEPROM structure. The EEPROM structure belongs to the semiconductor manufacture technology field, and comprises a semiconductor substrate, and a metal oxide semiconductor (MOS) capacitor, a polysilicon capacitor, an MOS selectron and an MOS reading tube which are formed on the semiconductor substrate. The capacitance value of the polysilicon capacitor is greater than the capacitance value of the MOS capacitor. The EEPROM structure is low in working voltage, thereby being able to improve the data storage capability, and possessing the high reliability, durability and data security.

Description

technical field [0001] The invention relates to a semiconductor storage device, in particular to an EEPROM storage device. Background technique [0002] RFID tags have been widely used in goods supply management, package tracking and identification, logistics warehousing, mobile commerce, aviation and medical services. The passive RFID tag chip includes radio frequency, logic and memory modules, where the memory module provides information storage space for product identification, transmission, catalog list and user information. In the prior art, EEPROM has a competitive advantage over Ferroelectric Random Access Memory (FeRAM) in terms of read operation, because its read operation does not destroy information and does not need to be rewritten after reading. In addition, its compatibility with the CMOS process is also better than the latter, which is convenient for large-scale industrial production and helps reduce costs. [0003] The passive RFID tag chip has no power sup...

Claims

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Application Information

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IPC IPC(8): H01L27/115
Inventor 陈龙
Owner 合肥矽景电子有限责任公司
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