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Cell with anti-PID effect and preparation method thereof

A cell and effect technology, applied in circuits, electrical components, final product manufacturing, etc., can solve the problems of little anti-PID effect, low cost input and practicability, thermal damage to the surface of silicon wafers, etc., and achieve process stability. Good reproducibility and repeatability, delay PID effect, reduce the effect of compound center

Inactive Publication Date: 2015-03-11
CECEP SOLAR ENERGY TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Some manufacturers also grow a layer of silicon dioxide film on the surface of the cell through high-temperature thermal oxidation to delay the occurrence of the PID effect. Due to the complex operation, low yield, high energy consumption, and serious thermal damage on the surface of the silicon chip, this process and many other problems prevent it from being widely adopted
[0004] In terms of components and packaging materials, some manufacturers are also trying to improve the PID effect by adjusting the composition of EVA film, glass and other materials at the expense of light transmittance and other properties of materials, but most of these methods have paid a large price. However, its anti-PID effect has little effect, and its low cost and practicality make it difficult to promote and use it in the production line.

Method used

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  • Cell with anti-PID effect and preparation method thereof
  • Cell with anti-PID effect and preparation method thereof
  • Cell with anti-PID effect and preparation method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0024] Embodiment 1: An anti-PID effect cell, comprising a crystalline silicon substrate after etching and cleaning, an anti-PID protective layer and a passivation anti-reflection layer sequentially deposited thereon. Among them, the anti-PID protective layer is a silicon-oxygen bonded Si-O thin layer, such as figure 1 As shown, Si-bonds an oxygen atom O provided by ozone on the dangling bond of Si on the surface of the crystalline silicon substrate to form a Si-O bond, and the thickness of the Si-O thin layer is 0.6 nm. The passivating antireflection layer is deposited by a tubular coating deposition process.

[0025] The manufacturing process of the above-mentioned anti-PID effect battery sheet comprises the following steps:

[0026] (1) Etching and cleaning the crystalline silicon substrate;

[0027] (2) Pretreatment: feed nitrogen for 50s, nitrogen flow rate is 8slm;

[0028] (3) Depositing an anti-PID protective layer: at a low temperature environment of 25°C, the pret...

Embodiment 2

[0034] Embodiment 2: roughly the same as Embodiment 1, the difference is that in the manufacturing process of the battery sheet: step (2) pretreatment, nitrogen gas is introduced for 80 s, and the nitrogen flow rate is 10 slm; step (3) low-temperature environment for depositing an anti-PID protective layer At 0°C, the pretreated crystalline silicon substrate is placed in an ozone environment with a concentration of 0.3% and a pressure of 1.5 standard atmospheric pressure, and the surface is strongly oxidized to form a silicon-oxygen bonded Si-O thin layer , reaction time 30s; step (4) deposition of passivation anti-reflection layer: ammonia gas flow rate: 2slm, silane flow rate: 200sccm, radio frequency power 4000W, deposition time 50s.

Embodiment 3

[0035] Embodiment 3: roughly the same as Embodiment 1, the difference is that in the manufacturing process of the battery sheet: step (2) pretreatment, nitrogen gas is passed through for 100s, and the flow rate of nitrogen gas is 7slm; step (3) low-temperature environment for depositing an anti-PID protective layer At 50°C, the pretreated crystalline silicon substrate is placed in an ozone environment with a concentration of 1.5% and a pressure of 1 standard atmosphere, and the surface is strongly oxidized to form a silicon-oxygen bonded Si-O thin layer , reaction time 1s; step (4) deposition of passivation anti-reflection layer: ammonia gas flow rate: 9slm, silane flow rate: 1900sccm, radio frequency power 7500W, deposition time 1000s.

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Abstract

Disclosed in the invention is a cell with an anti-PID effect and a preparation method thereof. The cell comprises a crystalline silica substrate after etching and cleaning, an anti-potential-induced-degradation (PID) protection layer, and a passivation anti-reflection layer, wherein the anti-PID protection layer and the passivation anti-reflection layer are successively deposisted on the crystalline silica substrate; and the anti-PID protection layer is a silicon-oxygen (Si-O) bond compound thin layer. According to the invention, because of protection from the anti-PID thin layer containing the Si-O bond, the cell has the excellent anti-PID effect; and thus no negative effects on the efficiency, appearance, and yield of the products and the like are caused. With the Si-O bond thin layer, the PID effect occurrence can be prevented and delayed, effective saturation of the suspension bond of the cell surface is also realized, and the recombination center of the cell surface can be reduced, so that the electrical performance of the cell can be improved to the certain extent.

Description

technical field [0001] The invention relates to the field of solar cell manufacturing technology, in particular to a battery sheet resistant to PID effect. Background technique [0002] With the continuous increase of photovoltaic installed capacity, a series of problems have appeared in the application process of photovoltaic power generation. Among them, the problem that has the greatest impact on the operation of the power station is the power drop of components due to potential induced degradation (PID). The power generation is reduced, and the PID phenomenon refers to the phenomenon that the photovoltaic performance of the module continues to decline due to the high voltage between the battery in the crystalline silicon photovoltaic module and its grounded metal frame. In the actual grid-connected photovoltaic system, the maximum power point voltage of the photovoltaic array, the grid voltage and the topological structure of the inverter determine the voltage (magnitude...

Claims

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Application Information

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IPC IPC(8): H01L31/0216H01L31/18
CPCH01L31/02168H01L31/02366H01L31/18Y02P70/50
Inventor 黄青松范维涛勾宪芳
Owner CECEP SOLAR ENERGY TECH