Method for treating ILD (injection laser diode) layer in gate-last technology

Abstract

The invention provides a method for treating an ILD (injection laser diode) layer in a gate-last technology. The method comprises the following steps of forming a pseudo gate region; covering an interlayer dielectric layer; performing chemico-mechanical polishing until a pseudo gate electrode is exposed; performing thermal annealing; and removing the pseudo gate region. Thermal annealing is carried out after the ILD layer is formed, the density of the ILD layer can be improved by a thermal annealing process, and the etching rate of the ILD layer can be reduced when the pseudo gate dielectric layer is removed, so that loss of the ILD layer is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for processing an ILD layer in a gate-last process. Background technique [0002] At present, the research on the manufacturing process of CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor) can be roughly divided into two directions, namely, the front gate process and the gate replacement process. Previously, all high-temperature annealing processes limited and could negatively impact gate layer material selection. The gate replacement process (gate last process, Gate Last), such as figure 1 As shown, the dummy gate 104, the dummy gate dielectric layer 102, the source and drain electrodes 105, and the ILD (interlayer dielectric) layer 106 are first formed, and then the dummy gate 104 is removed to form the gate again. In this way, the gate is formed after the source and drain, In this process, the gate does not need to withstand a high ...

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Problems solved by technology

[0003] In the usual gate-last process, after forming the dummy gate structure and the ILD layer, CMP is first performed until the dummy gate is exposed, then the dummy gate and the dummy gate dielectric layer are removed, and then the gate dielectric layer is re-formed. The dummy gate dielectric layer is usually Thermal oxide formation, ILD is mostly an oxide layer formed by CVD (Chemical Vapor Deposition, chemical vapor deposition) and other methods, dHF (diluted HF, diluted hydrofluoric acid) or dBOE (diluted HF) is usually used to remove the dummy gate dielectric layer Buffered Oxide Etch, diluted buffer solution), due to the different preparation methods, the density of the dummy gate dielectric layer and the ILD is also different, that is, the ILD has a faster etching rate, which will cause the loss of the ILD layer 106, such as figure 2 As shown, in this process, the removal of CMP and the dummy gate dielectric layer will cause the loss of ILD. The loss of ILD will affect the height of the re-formed replacement gate and reduce the normal performance of the device. If it is not handled properly, the device may even fail to work.

Since the process window of CMP is very small and difficult to control, in the actual process, the height of the dummy gate is often used to make up for the loss of ILD, but with the continuous reduction of process size, this method cannot solve the problem of ILD loss question

Especially in Fin-FET (Fin Field Effect Transistor) 3D devices, because there is no silicon nitride layer on the top of the device fin, CMP control is more difficult, and in order to obtain the ideal shape of the fin, a thicker dummy gate is usually formed Dielectric layer, which will inevitably increase the time to remove the dummy gate dielectric layer, which will cause more obvious ILD loss, and then it is difficult to obtain the ideal gate height, affecting the performance of the device

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