HEMT device with polarize junction longitudinal leakage current barrier lay structure and preparation method thereof
A technology of leakage current and barrier layer, which is applied in semiconductor/solid-state device manufacturing, electrical components, semiconductor devices, etc., can solve the problems of increased gate channel on-resistance, device threshold voltage stability and reliability issues, etc., to achieve Improve the breakdown voltage, reduce the longitudinal leakage current, and reduce the effect of device on-resistance
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Embodiment 1
[0037] A HEMT device with a polarized junction vertical leakage current blocking layer structure, the schematic diagram of its cross-sectional structure is as follows figure 1 shown.
[0038] The basic composition of the wafer structure from bottom to top is: substrate, which can be Si, SiC, sapphire, GaN, diamond, etc.; buffer layer on the substrate, which can be AlN or AlGaN superlattice structure; drift layer, that is, unintentional Doped i-GaN; polarized junction, that is, the composite structure of the lower AlGaN back barrier layer and the upper p-GaN layer; the channel layer, that is, the i-GaN layer; the main barrier layer, that is, the upper AlGaN layer.
[0039] Its structural characteristics are:
[0040] (1) The 2DEG channel in the gate region is completely cut off, and the device gate current conduction channel is vertical, and it works by applying a positive gate voltage to accumulate channel electrons;
[0041] (2) The source and drain electrodes are ohmic con...
Embodiment 2
[0048] A method for preparing a HEMT device with a polarized junction vertical leakage current blocking layer structure;
[0049] Step ①: wafer growth.
[0050] Using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) and other semiconductor material growth technologies to sequentially grow buffer layers, 2-10μm i-GaN layers, 5 -100nm AlGaN layer (Al composition is 0.05-0.2), 30-300nm P-GaN layer, 100-300nm i-GaN layer and 10-30nm AlGaN layer (Al composition is 0.1-0.35), such as figure 2 shown.
[0051] Step ②: mesa etching.
[0052] Use semiconductor lithography technology and semiconductor etching technology to produce the mesa required for the device, and use semiconductor etching technology such as reaction-coupled plasma (ICP) based on Cl-based gas to etch the surface by 300-800nm to achieve mesa isolation. Such as image 3 shown. Among them, the semiconductor photolithography technology includes complete steps such as glue leveling, ...
Embodiment 3
[0064] A method for preparing a HEMT device with a polarized junction vertical leakage current blocking layer structure;
[0065] Step ①: wafer growth.
[0066] A 100nm AlN buffer layer, a 4μm GaN layer, and a 10nm Al 0.1 Ga 0.9 N layer, 50nm p-GaN layer, 100nm intrinsic GaN layer and 20nm Al 0.25 Ga 0.75 N layers.
[0067] Step ②: mesa etching.
[0068] Using semiconductor lithography technology to define the required area of the barrier layer, the process is:
[0069] (1) Evenly spin coat the sample with AZ5214 photoresist at a rate of 4000r / min for 30s;
[0070] (2) Place the sample on a hot plate at 100°C for soft drying for 90s;
[0071] (3) Place the sample at a light intensity of 7mW / cm 2 Expose continuously for 20s in the left and right exposure machines;
[0072] (4) develop in developer for 45s;
[0073] (5) Heat the hardened film on a hot plate at 100°C for 60s. Then, through the ICP etching technology based on Cl-based gas, the mesa required for the de...
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