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Manufacture of high electron transference rate transistors with nano T grids

A technology with high electron mobility and manufacturing method, which is applied in the field of nano T-gate manufacturing, can solve the problems of high manufacturing cost, complexity, and complicated process

Inactive Publication Date: 2006-09-27
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Generally, electron beam lithography or X-ray lithography is used to produce deep submicron grid lengths. As we all know, these processes are very complicated. If a finer grid length is to be obtained, the manufacturing cost will be higher and the process will be more complicated.

Method used

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  • Manufacture of high electron transference rate transistors with nano T grids
  • Manufacture of high electron transference rate transistors with nano T grids
  • Manufacture of high electron transference rate transistors with nano T grids

Examples

Experimental program
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Effect test

Embodiment

[0034] like Figure 2-1 As shown, firstly, a photoresist is coated on the PHEMT or MESFET sheet 201 and exposed, the thickness of the photoresist is 2 μm, and the photoresist pattern 202 of the active island area is formed after development;

[0035] like Figure 2-2 As shown, the photoresist pattern 202 in the active island region is used as a mask, and double protons or oxygen and boron ions are implanted to form an isolation region 203 (the mesa can also be obtained by a wet method, that is, the photoresist pattern 202 is used as a mask, with Phosphoric acid: hydrogen peroxide: deionized water=3:1:60 formula to corrode the conductive layer of isolation area 203);

[0036] like Figure 2-3 As shown, source-drain pattern by photolithography: apply S9912 photoresist with a thickness of 1 μm, after exposure, reverse ammonia at 100°C for 2 minutes, then flood-expose the surface of the film, and use phosphoric acid: deionized after development Water = 1:10 soak for 50 seconds...

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Abstract

The technique includes following steps: 1. photoetching figure of active region on wafer of gallium arsenide heterojunction etc. 2. preparing table top through ion implantation or wet-process corrosion; 3. depositing insulation layer; 4. photoctching grating graph; 5. anisotropic etching insulation layer; 6. isotropic etching insulation layer; 7. coating photoresist on substrate; 8. thinning down photoresist on substrate; 9. forming wide grating window covered on grating groove through conventional photoetching; 10. removing figure of insulation layer; 11. etching N+ area under grating grooves within window; 12. vaporizing and removing off grating metal; 13. passivating and opening window formed through connected lines, and completing fabrication of parts.

Description

technical field [0001] The invention belongs to the field of microfabrication in semiconductor technology, in particular to a method for manufacturing a nanometer T-shaped gate of a high electron mobility transistor. It is characterized by shortening the gate length of the high electron mobility transistor and obtaining a T-shaped gate structure by using the method of line compression, which has strong practical value. Background technique [0002] For Gallium Arsenide Metal Semiconductor Field Effect Transistor (GaAs MESFET), Gallium Arsenide Pseudomeric High Electron Mobility Transistor (GaAs PHEMT) and Indium Phosphide Pseudomeric High Electron Mobility Transistor (InP PHEMT), in order to increase their cut-off frequency , the gate length must be shortened. In order to reduce the gate resistance while shortening the gate length, it is usually necessary to adopt a T-shaped gate structure. Electron beam lithography or X-ray lithography is generally used to fabricate deep s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/335
Inventor 谢常青叶甜春陈大鹏李兵
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI