Method for electrochemical plating on semiconductor wafers

Abstract

A method of electroplating conductive material on semiconductor wafers improves deposited film quality by providing greater control over the formation of the film grain structure. Better grain size control is achieved by applying a continuous DC plating current to the wafer which avoids sharp discontinuities in the current as the applied current is increased in successive stages during a plating cycle. Current discontinuities are avoided by gradually increasing the current in a ramp-like fashion between the successive plating stages.

Description

FIELD OF THE INVENTION [0001] This invention generally relates to electrodeposition of conductive films on semiconductor wafers, and deals more particularly with an improved method of controlling the electroplating current in order to better control grain size and improve film quality. BACKGROUND OF THE INVENTION [0002] Many typical phototolithographic integrated circuit chip fabrication processes include a deposition phase in which material of different electrical characteristics is deposited in a space created in a diffusion material. Deposition phases of lithographic processes are often utilized to create components such as resistors, diodes and transistors, and electrical interconnections between components. Current technology electrical connections often include lines and plugs that are deposited in dielectric layers of the wafer. In the past, lines typically comprised aluminum, or an aluminum alloy, and plugs included tungsten. However, as component sizes become smaller and mo...

AI Technical Summary

Benefits of technology

[0009] As a result of the gradual increase of the current between successive stages, a more uniform and continuous grain structure is achieved throughout the plated film. As a result of the more uniform grain structure, thermal stresses within the film are reduced, and overall film quality is improved.

Problems solved by technology

However, as component sizes become smaller and more layers of metallization are fabricated, interconnections comprising copper are becoming more prevelant.

Copper interconnect electrodeposition faces a number of challenges in the form of non-uniformity of the copper layer over the wafer and filling small, high aspect ratio contactless without void formation.

The electrical current is switched almost instantly from one level to another as one stage is finished and the next stage is commenced, resulting in a step-like discontinuity in the applied current waveform.

Sharp changes in grain size, and thus of resistivity, is undesirable for a number of reasons, including the creation of unbalanced thermal stresses, for example that can result in defects such as so called “edge pullback.” Edge pullback is a phenomenon where low or sometimes no copper plating occurs on the edges of adjacent surface features.

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